US4323638A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Reducing charging effects in charged-particle-beam lithography
Assignee: AT&T Inc
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Filing: 1980-08-18
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Granted: 1982-04-06
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Expires: 2000-08-18
Abstract
Abstract In a charged-particle-beam lithographic system, charge accumulation on the workpiece during alignment or writing can cause significant pattern placement errors. A film (16) formed directly under the resist layer (56) to be patterned is utilized as a charge-conducting medium during lithography. The pattern delineated in the resist layer (56) is transferred into the film (16) and subsequently into an underlying layer (20). The film (16) is highly compatible with standard lithographic and etching processes used to fabricate LSI and VLSI circuits.
Inventors
- 👤 Arthur C. Adams
- 👤 Frank B. Alexander, Jr.
- 👤 Hyman J. Levinstein
- 👤 Louis R. Thibault
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 00:19
CPC Classifications
H; H10; H10P; H10P76/00; H10P76/20; H10P76/204; H10P76/2045; Y; Y10; Y10S; Y10S430/00; Y10S430/143
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
158 words
A method of fabricating integrated circuits by patterning a resist layer by means of a charged-particle beam in a high-resolution lithographic system, said method comprising the steps of forming on one main surface of a wafer a layer to be patterned, depositing a continuous charge-conducting film on top of said layer to be patterned, on the sides of said wafer and on at least a peripheral portion of the other main surface of said wafer, depositing a resist layer on top of the portion of said charge-conducting film that overlies the main surface of said wafer, mounting said wafer in a cassette holder to establish an electrical connection between the peripheral portion of said charge-conducting film and a part of said holder that is connected to a point of reference potential, and, while said wafer is so mounted in said cassette holder, delineating a pattern in said resist layer by directing a charged-particle beam at said resist layer.
Claim 2
Independent Claim
158 words
A method of fabricating integrated circuits by patterning a resist layer by means of a charged-particle beam in a high-resolution lithographic system, said method comprising the steps of forming on one main surface of a wafer a layer to be patterned, depositing a continuous charge-conducting film on top of said layer to be patterned, on the sides of said wafer and on at least a peripheral portion of the other main surface of said wafer, depositing a resist layer on top of the portion of said charge-conducting film that overlies the main surface of said wafer, mounting said wafer in a cassette holder to establish an electrical connection between the peripheral portion of said charge-conducting film and a part of said holder that is connected to a point of reference potential, and, while said wafer is so mounted in said cassette holder, delineating a pattern in said resist layer by directing a charged-particle beam at said resist layer.
Claim 3
Dependent Claim
36 words
A method as in claim 1 further including the steps of transferring the pattern delineated in said resist layer into said charge-conducting film, and transferring the pattern in said film into said layer to be patterned.
Claim 4
Dependent Claim
26 words
A method as in claim 2 wherein said layer to be patterned comprises a relatively thick sacrificial layer having a top surface that is essentially planar.
Claim 5
Dependent Claim
21 words
A method as in claim 3 wherein said charge-conducting film comprises a plasma-deposited boron-doped polysilicon film approximately 500-to-1000 Angstrom units thick.
Claim 6
Independent Claim
51 words
A method of fabricating integrated circuits comprising the steps of forming on one main surface of a wafer a layer to be patterned, forming a plasma-deposited boron-doped polysilicon film exhibiting charge-conducting properties on top of said layer to be patterned, and depositing a resist layer on top of said charge-conducting film.
Claim 7
Independent Claim
51 words
A method of fabricating integrated circuits comprising the steps of forming on one main surface of a wafer a layer to be patterned, forming a plasma-deposited boron-doped polysilicon film exhibiting charge-conducting properties on top of said layer to be patterned, and depositing a resist layer on top of said charge-conducting film.
Claim 8
Dependent Claim
32 words
A method as in claim 5 wherein said charge-conducting film is also formed on the sides of said wafer and on a peripheral portion of the other main surface of said wafer.
Claim 9
Dependent Claim
64 words
A method as in claim 6 further including the steps of mounting said wafer in a holder in a charged-particle-beam lithographic system to establish an electrical connection between the peripheral portion of said charge-conducting film and a point of reference potential, and, while said wafer is so mounted, delineating a pattern in said resist layer by directing a charged-particle beam at said resist layer.
Claim 10
Dependent Claim
36 words
A method as in claim 7 further including the steps of transferring the pattern delineated in said resist layer into said charge-conducting film, and transferring the pattern in said film into said layer to be patterned.
Claim 11
Independent Claim
134 words
A method of fabricating integrated circuits by patterning a resist layer (56) by means of a charged-particle beam in a high-resolution lithographic system, said method comprising the steps of forming on one main surface of a wafer (18) a layer (20) to be patterned, and delineating a pattern in said resist layer (56) by directing a charged-particle beam at said resist layer (56), characterized in that said method comprises the steps of depositing a charge-conducting film (16) on top of said layer (20) to be patterned, on the sides of said wafer (18) and on at least a peripheral portion of the other main surface of said wafer (18), said resist layer (56) being deposited on top of the portion of said charge-conducting film (16) that overlies the main surface of said wafer (18).
Claim 12
Independent Claim
134 words
A method of fabricating integrated circuits by patterning a resist layer (56) by means of a charged-particle beam in a high-resolution lithographic system, said method comprising the steps of forming on one main surface of a wafer (18) a layer (20) to be patterned, and delineating a pattern in said resist layer (56) by directing a charged-particle beam at said resist layer (56), characterized in that said method comprises the steps of depositing a charge-conducting film (16) on top of said layer (20) to be patterned, on the sides of said wafer (18) and on at least a peripheral portion of the other main surface of said wafer (18), said resist layer (56) being deposited on top of the portion of said charge-conducting film (16) that overlies the main surface of said wafer (18).
Claim 13
Independent Claim
93 words
A method of fabricating integrated circuits comprising the steps of forming on one main surface of a wafer a layer to be patterned, forming a charge-conducting film on top of said layer to be patterned, depositing a resist layer on top of said charge-conducting film, delineating a pattern in said resist layer by directing a charged-particle beam at said resist layer, transferring the pattern delineated in said resist layer into said charge-conducting film, and, utilizing said patterned film as a mask, transferring the pattern in said film into said layer to be patterned.
Claim 14
Independent Claim
93 words
A method of fabricating integrated circuits comprising the steps of forming on one main surface of a wafer a layer to be patterned, forming a charge-conducting film on top of said layer to be patterned, depositing a resist layer on top of said charge-conducting film, delineating a pattern in said resist layer by directing a charged-particle beam at said resist layer, transferring the pattern delineated in said resist layer into said charge-conducting film, and, utilizing said patterned film as a mask, transferring the pattern in said film into said layer to be patterned.
Claim 15
Dependent Claim
26 words
A method as in claim 10 wherein said layer to be patterned comprises a relatively thick sacrificial layer having a top surface that is essentially planar.
Claim 16
Dependent Claim
15 words
A method as in claim 11 wherein said charge-conducting film comprises a doped polysilicon film.
Claim 17
Dependent Claim
20 words
A method as in claim 12 wherein said film comprises a plasma-deposited boron-doped polysilicon film approximately 500-to-1000 Angstrom units thick.
Claim 18
Dependent Claim
32 words
A method as in claim 10 wherein said charge-conducting film is also formed on the sides of said wafer and on a peripheral portion of the other main surface of said wafer.
Claim 19
Dependent Claim
95 words
A method as in claim 14 further including the steps of mounting said wafer in a holder in a charged-particle-beam lithographic system to establish an electrical connection between the peripheral portion of said charge-conducting film and a point of reference potential, while said wafer is so mounted, delineating a pattern in said resist layer by directing a charged-particle beam at said resist layer, transferring the pattern delineated in said resist layer into said charge-conducting film, and, utilizing said patterned film as a mask, transferring the pattern in said film into said layer to be patterned.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-04-05 | 1985-10-05 | 1986-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-04-05 | 1989-10-05 | 1990-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-04-05 | 1993-10-05 | 1994-04-06 | $7700.00 | Window Closed / Lapsed |