Input stage using junction field effect transistors for biasing
Abstract
Abstract In a bias circuit including at least a pair of bipolar transistors interconnected to function as active loads, two junction field effect transistors are interconnected such that the source of one transistor is connected to the emitter of the first of the pair of bipolar transistors and the source of the second junction field effect transistor is connected to the emitter of the second of said bipolar transistors, and the gate electrodes of the first and second junction field effect transistors are electrically connected to each other and to the drain electrodes of both the first and second junction field effect transistors. Alternatively, the drain electrodes of the first and second junction field effect transistors are connected to a common bus and the gate electrodes are connected to a low impedance node.
Inventors
- 👤 James R. Butler
Bibliographic Details
Claims Analysis
Total Claims: 4References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-02-15 | 1985-08-17 | 1986-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-02-15 | 1989-08-17 | 1990-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-02-15 | 1993-08-17 | 1994-02-16 | $7700.00 | Window Closed / Lapsed |