Patent US4313255A successfully refreshed from Google Patents.
US4313255A
Expired / Lapsed
US
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Method for manufacturing integrated circuit device
Assignee: Toshiba Corp
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Filing: 1979-12-21
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Granted: 1982-02-02
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Expires: 1999-12-21
Abstract
Abstract Disclosed is a method for manufacturing an integrated circuit device which comprises the steps of preparing a silicon substrate having an isolated first region of a first conductivity type, selectively forming on the first region a polycrystalline silicon layer containing an impurity of the first conductivity type, implanting the first region including the polycrystalline silicon layer with an ion of an impurity of a second conductivity type having higher diffusion coefficient than that of the impurity of the first conductivity type, and heating the substrate, whereby the implanted impurity of the second conductivity type is diffused into the first region to form a second region of the second conductivity type and the impurity of the first conductivity type in the polycrystalline silicon layer is diffused into the second region to form a third region of the first conductivity type.
Inventors
- 👤 Satoshi Shinozaki
- 👤 Shinzi Saito
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:06
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/051; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; H10P76/00; H10P76/40
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
226 words
A method for manufacturing an integrated device comprising the steps of preparing a semiconductor substrate having an isolated region of a first conductivity type; forming on a selected portion of said isolated region a polycrystalline silicon layer containing a dopant impurity of said first conductivity type; forming a silicon dioxide layer over the isolated region, including said doped polycrystalline silicon layer, subjecting the isolated region, including the silicon dioxide layer and the doped polycrystalline silicon layer, to an ion implantation of an impurity of a second conductivity type having a higher diffusion coefficient than that of the impurity of said first conductivity type, to thereby implant an impurity of said second conductivity type into said layers; heating said substrate and said layers for a sufficient period to diffuse the impurities of the first and second types to said substrate, whereby the impurity of the first type diffuses into the substrate below the polycrystalline silicon layer to form a first region of first conductivity type, the ion-implanted impurity of the second type diffuses into the substrate below the polycrystalline silicon layer and beyond said first region to form a second region of second conductivity type, and the ion impurity of the second type implanted in the silicon dioxide layer diffuses into the substrate below said silicon dioxide layer to form a third region of second conductivity type.
Claim 2
Independent Claim
226 words
A method for manufacturing an integrated device comprising the steps of preparing a semiconductor substrate having an isolated region of a first conductivity type; forming on a selected portion of said isolated region a polycrystalline silicon layer containing a dopant impurity of said first conductivity type; forming a silicon dioxide layer over the isolated region, including said doped polycrystalline silicon layer, subjecting the isolated region, including the silicon dioxide layer and the doped polycrystalline silicon layer, to an ion implantation of an impurity of a second conductivity type having a higher diffusion coefficient than that of the impurity of said first conductivity type, to thereby implant an impurity of said second conductivity type into said layers; heating said substrate and said layers for a sufficient period to diffuse the impurities of the first and second types to said substrate, whereby the impurity of the first type diffuses into the substrate below the polycrystalline silicon layer to form a first region of first conductivity type, the ion-implanted impurity of the second type diffuses into the substrate below the polycrystalline silicon layer and beyond said first region to form a second region of second conductivity type, and the ion impurity of the second type implanted in the silicon dioxide layer diffuses into the substrate below said silicon dioxide layer to form a third region of second conductivity type.
Claim 3
Dependent Claim
47 words
The method according to claim 1 wherein said impurities of said first and second conductivity types are arsenic and boron, respectively, and wherein said first region is an emitter region, said second region is an interior base region, and said third region is an exterior base region.
Claim 4
Dependent Claim
29 words
The method according to claim 1 wherein said silicon dioxide layer formed over said polycrystalline silicon layer is thicker than the silicon dioxide layer formed directly on the substrate.
Claim 5
Dependent Claim
13 words
The method according to claim 3 wherein said substrate is a silicon substrate.
Claim 6
Independent Claim
243 words
A method for manufacturing an integrated circuit device with a bipolar transistor comprising: preparing a silicon substrate having an isolated region of a first conductivity type; forming on a selected portion of said isolated region a polycrystalline silicon layer containing a dopant impurity of said first conductivity type; forming a silicon dioxide layer over the isolated region, including said doped polycrystalline silicon layer, for controlling the formation of the emitter and base regions of the bipolar transistor; subjecting the isolated region, including the silicon dioxide layer and the doped polycrystalline silicon layer, to an ion implantation of an impurity of a second conductivity type having a higher diffusion coefficient than that of the impurity of said first conductivity type, to thereby implant an impurity of said second conductivity type into said layers; heating said substrate and said layers for a sufficient period to diffuse the impurities of the first and second types into said substrate, whereby the impurity of the first type diffuses into the substrate below the polycrystalline silicon layer to form a first region of first conductivity type, the ion-implanted impurity of the second type diffuses into the silicon substrate below the polycrystalline silicon layer and beyond said first region to form a second region of second conductivity type, and the ion impurity of the second type implanted in the silicon dioxide layer diffuses into the substrate below said silicon dioxide layer to form a third region of second conductivity type.
Claim 7
Independent Claim
243 words
A method for manufacturing an integrated circuit device with a bipolar transistor comprising: preparing a silicon substrate having an isolated region of a first conductivity type; forming on a selected portion of said isolated region a polycrystalline silicon layer containing a dopant impurity of said first conductivity type; forming a silicon dioxide layer over the isolated region, including said doped polycrystalline silicon layer, for controlling the formation of the emitter and base regions of the bipolar transistor; subjecting the isolated region, including the silicon dioxide layer and the doped polycrystalline silicon layer, to an ion implantation of an impurity of a second conductivity type having a higher diffusion coefficient than that of the impurity of said first conductivity type, to thereby implant an impurity of said second conductivity type into said layers; heating said substrate and said layers for a sufficient period to diffuse the impurities of the first and second types into said substrate, whereby the impurity of the first type diffuses into the substrate below the polycrystalline silicon layer to form a first region of first conductivity type, the ion-implanted impurity of the second type diffuses into the silicon substrate below the polycrystalline silicon layer and beyond said first region to form a second region of second conductivity type, and the ion impurity of the second type implanted in the silicon dioxide layer diffuses into the substrate below said silicon dioxide layer to form a third region of second conductivity type.
Claim 8
Dependent Claim
47 words
The method according to claim 5 wherein said impurities of said first and second conductivity types are arsenic and boron, respectively, and wherein said first region is an emitter region, said second region is an interior base region, and said third region is an exterior base region.
Claim 9
Dependent Claim
91 words
The method according to claim 6 further comprising the steps of: selectively removing a portion of the silicon dioxide layer directly over said polycrystalline silicon layer to form a first contact hole; removing a portion of the silicon dioxide layer directly over said isolated region of said substrate to form a second contact hole; and attaching electrodes at said first and second contact holes directly to said polycrystalline silicon layer and said silicon substrate, respectively, whereby said polycrystalline layer acts as a conductor connecting the emitter electrode and the emitter region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-02-01 | 1985-08-03 | 1986-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-02-01 | 1989-08-03 | 1990-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-02-01 | 1993-08-03 | 1994-02-02 | $7700.00 | Window Closed / Lapsed |