Patent US2090886A successfully refreshed from Google Patents.
Patent US4313253A successfully refreshed from Google Patents.
US4313253A
Expired / Lapsed
US
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Method of fabricating a charge transfer channel covered by a stepped insulating layer
Assignee: Samsung Electronics Co Ltd
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Filing: 1980-01-18
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Granted: 1982-02-02
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Expires: 2000-01-18
Abstract
Abstract The disclosed memory cell is comprised of a charge storage region and an adjacent charge transfer channel. A deep dopant layer extends throughout the charge storage region, and a shallow dopant layer extends throughout the charge storage region plus part-way through the charge transfer channel. Overlying the charge storage region is a first conductor that is completely covered by a thick insulating layer. This thick insulating layer also extends into the charge transfer channel part-way over the shallow dopant layer. A thin insulating layer covers the remaining portion of the channel. Lying on this thin insulating layer and extending onto the thick insulating layer is a second conductor. Parasitic capacitance and catastrophic shorts between the two conductors are minimized by the thick insulating layer; charge storage capacity of the storage region is maximized by the two dopant layers lying therein; and cell length is minimized by the thick insulating layer and underlying shallow dopant layer in the charge transfer channel.
Inventors
- 👤 Donald L. Henderson, Sr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 14:15
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10B12/30
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
232 words
A method of fabricating a memory cell on a semiconductor substrate comprised of dopant impurity atoms of a first type and having a first surface, including the steps of: defining a charge storage region and an adjacent charge transfer channel in said substrate near said first surface; introducing a deep layer of dopant impurity atoms of said first type throughout said charge storage region; introducing a shallow layer of dopant impurity atoms of a second type opposite to said first type throughout said charge storage region and also extending therefrom into a first adjacent portion of said charge transfer channel; forming a relatively thin insulating layer over said charge storage region; forming a first patterned conductor on said relatively thin insulating layer over said charge storage region; forming a relatively thick insulating layer over said first patterned conductor, and also extending therefrom over a second adjacent portion of said charge transfer channel that lies within said first adjacent portion so that said shallow layer of dopant impurity atoms lies under and extends beyond said relatively thick insulating layer in said charge transfer channel; forming a relatively thin insulating layer over that portion of said charge transfer channel which is not covered by said relatively thick insulating layer; and forming a second patterned conductor on said relatively thin insulating layer over said charge transfer channel and extending onto said relatively thick insulating layer.
Claim 2
Independent Claim
232 words
A method of fabricating a memory cell on a semiconductor substrate comprised of dopant impurity atoms of a first type and having a first surface, including the steps of: defining a charge storage region and an adjacent charge transfer channel in said substrate near said first surface; introducing a deep layer of dopant impurity atoms of said first type throughout said charge storage region; introducing a shallow layer of dopant impurity atoms of a second type opposite to said first type throughout said charge storage region and also extending therefrom into a first adjacent portion of said charge transfer channel; forming a relatively thin insulating layer over said charge storage region; forming a first patterned conductor on said relatively thin insulating layer over said charge storage region; forming a relatively thick insulating layer over said first patterned conductor, and also extending therefrom over a second adjacent portion of said charge transfer channel that lies within said first adjacent portion so that said shallow layer of dopant impurity atoms lies under and extends beyond said relatively thick insulating layer in said charge transfer channel; forming a relatively thin insulating layer over that portion of said charge transfer channel which is not covered by said relatively thick insulating layer; and forming a second patterned conductor on said relatively thin insulating layer over said charge transfer channel and extending onto said relatively thick insulating layer.
Claim 3
Dependent Claim
59 words
A method according to claim 1 wherein said relatively thick insulating layer is formed by the substeps of: covering both said charge storage region and said charge transfer channel with said relatively thick insulating layer; and subsequently removing said relatively thick insulating layer from that portion of said charge transfer channel which lies outside of said second adjacent portion.
Claim 4
Dependent Claim
62 words
A method according to claim 1 wherein said relatively thick insulating layer is formed by the substeps of: covering that portion of said charge transfer channel which lies outside of said second adjacent portion with a masking material; and subsequently forming said relatively thick insulating layer on only those surfaces of said memory cell which are not covered by said masking material.
Claim 5
Dependent Claim
23 words
A method according to claim 1 wherein said first adjacent portion of said charge transfer channel is greater than 1.5 microns in length.
Claim 6
Dependent Claim
24 words
A method according to claim 1 wherein said relatively thick insulating layer is at least three times thicker than said relatively thin insulating layer.
Claim 7
Dependent Claim
24 words
A method according to claim 1 wherein sid first type dopant impurity atoms are P-type and said second type dopant impurity atoms are N-type.
Claim 8
Dependent Claim
24 words
A method according to claim 1 wherein said first type dopant impurity atoms are N-type and said second type dopant impurity atoms are P-type.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-02-01 | 1985-08-03 | 1986-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-02-01 | 1989-08-03 | 1990-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-02-01 | 1993-08-03 | 1994-02-02 | $7700.00 | Window Closed / Lapsed |