Patent US4313103A successfully refreshed from Google Patents.
US4313103A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital demodulator
Assignee: National Aeronautics and Space Administration
•
Filing: 1980-07-18
•
Granted: 1982-01-26
•
Expires: 2000-07-18
Abstract
Abstract A digital demodulator for converting PCM data from PSK to NRZ-L and to Biφ-L. The demodulator is composed of standard integrated logic circuits. The key to the demodulation function is a pair of cross-coupled one-shot multivibrators 11 and 12 which with a flip-flop 13 produce the NRZ-L. In order to generate Biφ-L, the PSK carrier is constrained to be 2 N times the data bit rate. If NRZ-L is all that is required, the circuitry is greatly simplified and the 2 N times bit rate constraint can be removed from the carrier. A flip-flop 15, an OR gate 14, and AND gate 16 and a binary counter 17 generate the bit rate clock BTCK for the NRZ-L. The remainder of the circuitry is for converting the NRZ-L and BTCK into Biφ-L.
Inventors
- 👤 Thomas A. Shull
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 18:35
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/233; H04L27/2335; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4904
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
180 words
A digital demodulator for converting PCM data from a 2 N bit rate carrier PSK signal to Biφ-L comprising: means receiving the PSK signals for generating NRZ-L data signals and bit clock signals; and means responsive to said NRZ-L signals and said bit clock signals for generating Biφ-L signals at a bit rate 1/2 N times the PSK rate; wherein said means for generating said NRZ-L data signals comprises: a first one-shot multivibrator that is activated on the leading edges of pulses applied to it, connected to receive said PSK signals; a second one-shot multivibrator, that is activated on the following edges of pulses applied to it, connected to receive said PSK signals; a flip-flop having its reset input connected to the normal output of said first one-shot multivibrator and having its set input connected to the normal output of said second one-shot multivibrators; and the inverted outputs of said first and second one-shot multivibrators connected to the reset input of the second and first one-shot multivibrators, respectively, whereby the normal output of the flip-flop is said NRZ-L data signals.
Claim 2
Dependent Claim
180 words
A digital demodulator for converting PCM data from a 2 N bit rate carrier PSK signal to Biφ-L comprising: means receiving the PSK signals for generating NRZ-L data signals and bit clock signals; and means responsive to said NRZ-L signals and said bit clock signals for generating Biφ-L signals at a bit rate 1/2 N times the PSK rate; wherein said means for generating said NRZ-L data signals comprises: a first one-shot multivibrator that is activated on the leading edges of pulses applied to it, connected to receive said PSK signals; a second one-shot multivibrator, that is activated on the following edges of pulses applied to it, connected to receive said PSK signals; a flip-flop having its reset input connected to the normal output of said first one-shot multivibrator and having its set input connected to the normal output of said second one-shot multivibrators; and the inverted outputs of said first and second one-shot multivibrators connected to the reset input of the second and first one-shot multivibrators, respectively, whereby the normal output of the flip-flop is said NRZ-L data signals.
Claim 3
Dependent Claim
29 words
A digital demodulator according to claim 1 wherein means are connected to receive the normal outputs of said first and second one-shot multivibrators for generating said bit clock signals.
Claim 4
Dependent Claim
130 words
A digital demodulator according to claim 2 wherein said means for generating said bit clock signals comprises: a binary counter; an OR gate connected to receive the normal outputs from said first and second one-shot multivibrators; a second flip-flop with its data input connected to the normal output of said first flip-flop and with its clock input connected to the output of said OR gate; an AND gate with its inputs connected to the normal output of said second flip-flop and to the inverted output of said first flip-flop; and a counter with its input connected to the output of said OR gate and with its reset connected to the output of said AND gate whereby the output of the Nth stage of said counter is said bit clock signals.
Claim 5
Dependent Claim
114 words
A digital demodulator according to claim 3 wherein said means for generating Biφ-L signals includes: a second AND gate with its inputs connected to the inverted output of said first flip-flop and to the output of the Nth stage of said counter; an inverter for inverting the output of the Nth stage of said counter; a third AND gate with its inputs connected to the normal output of said first flip-flop and the inverted output of the Nth stage of said counter; and a second OR gate with its two inputs connected to the outputs of said second and third AND gates whereby the output of said second OR gate is the Biφ-L signals.
Claim 6
Dependent Claim
61 words
A digital demodulator according to claim 4 wherein said means for generating Biφ-L signals further includes: a third flip-flop with its data input connected to the output of said second OR gate and with its clock input connected to the output of the (N-1) the stage of said counter whereby the normal output of said third flip-flop is the Biφ-L signals.
Claim 7
Dependent Claim
139 words
A digital demodulator for converting PCM data from PSK signals to NRZ-L signals and bit clock signals comprising: a first one-shot multivibrator that is activated on the leading edges of pulses applied to it, connected to receive said PSK signals; a second one-shot multivibrator that is activated on the following edges of pulses applied to it, connected to receive said PSK signals; the inverted outputs of said first and second one-shot multivibrators connected to the reset inputs of the second and first one-shot multivibrators, respectively; a flip-flop having its reset and set inputs connected to the normal outputs of said first and second one-shot multivibrators, respectively; whereby the normal output of said flip-flop is the NRZ-L signals; and means connected to the outputs of said first and second one-shot multivibrator and said flip-flop for generating said bit clock signals.
Claim 8
Dependent Claim
139 words
A digital demodulator for converting PCM data from PSK signals to NRZ-L signals and bit clock signals comprising: a first one-shot multivibrator that is activated on the leading edges of pulses applied to it, connected to receive said PSK signals; a second one-shot multivibrator that is activated on the following edges of pulses applied to it, connected to receive said PSK signals; the inverted outputs of said first and second one-shot multivibrators connected to the reset inputs of the second and first one-shot multivibrators, respectively; a flip-flop having its reset and set inputs connected to the normal outputs of said first and second one-shot multivibrators, respectively; whereby the normal output of said flip-flop is the NRZ-L signals; and means connected to the outputs of said first and second one-shot multivibrator and said flip-flop for generating said bit clock signals.
Claim 9
Dependent Claim
119 words
A digital demodulator according to claim 6 wherein said means for generating said bit clock signals comprise: an OR gate with its inputs connected to the normal outputs of said first and second one-shot multivibrators; a second flip-flop with its data input connected to the normal output of the first flip-flop and with its clock input connected to the output of said OR gate; an AND gate with its inputs connected to the normal output of said second flip-flop and to the inverted output of the first flip-flop; and a counter with its inputs connected to the outputs of said AND and OR gates whereby the output of the Nth stage of said counter is said bit clock signals.
References Cited (Backward Citations)
US3047853A
Cited
US3970945A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-01-25 | 1985-07-27 | 1986-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-01-25 | 1989-07-27 | 1990-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-01-25 | 1993-07-27 | 1994-01-26 | $7700.00 | Window Closed / Lapsed |