Patent US4752337A successfully refreshed from Google Patents.
Patent US4635033A successfully refreshed from Google Patents.
Patent US4309694A successfully refreshed from Google Patents.
US4309694A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Zero disparity coding system
Assignee: AT&T Inc
•
Filing: 1980-03-27
•
Granted: 1982-01-05
•
Expires: 2000-03-27
Abstract
Abstract In a digital transmission system, disparity is defined as the difference between the number of binary digits at each code state. The generation of a block of binary digits having zero disparity possesses many advantages. The present invention discloses coding apparatus (100, 300) for converting a block of binary digits having random disparity into a zero disparity block, and vice versa. The coder accomplishes this translation by determining (103) the disparity of the random disparity block and then selecting (103, 104, 106, 107, 110, 111) a bit position which divides the block into two digit segments each having half this disparity. Inversion (115) of either digit segment generates a zero disparity block. For decoding, data representing the bit position selected is transmitted along with the zero disparity block. The binary digits previously inverted by the coder are then reinverted. This coding/decoding technique is adaptable to any block size having an even number of binary digits.
Inventors
- 👤 Paul S. Henry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:09
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4906; H04L25/4915
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
86 words
Apparatus (100) for converting a first block (200) of n binary digits having random disparity to a second block (203, 204) having zero disparity, where n is an even number, CHARACTERIZED BY means (103) for determining the disparity of said first block; means (103, 104, 106, 107, 110, 111) for selecting a bit position within said first block which defines two digit segments each having half the disparity of said first block; and means (115) for inverting all of the digits within one of said segments.
Claim 2
Dependent Claim
86 words
Apparatus (100) for converting a first block (200) of n binary digits having random disparity to a second block (203, 204) having zero disparity, where n is an even number, CHARACTERIZED BY means (103) for determining the disparity of said first block; means (103, 104, 106, 107, 110, 111) for selecting a bit position within said first block which defines two digit segments each having half the disparity of said first block; and means (115) for inverting all of the digits within one of said segments.
Claim 3
Dependent Claim
17 words
The apparatus of claim 1 wherein said bit position is represented by a series of binary digits.
Claim 4
Dependent Claim
21 words
The apparatus of claim 2 further including translation means (119) for converting said series of binary digits into zero disparity format.
Claim 5
Dependent Claim
24 words
The apparatus of claim 3 further including means (111, 121, 122) for multiplexing said zero disparity block and the converted series of binary digits.
Claim 6
Dependent Claim
104 words
Decoder apparatus (300) for generating a block (200) of n binary digits having random disparity from a block (203) of n binary digits having zero disparity, where n is an even number, and data representing a bit position within said zero disparity block which defines two digit segments (201, 202) each having half the disparity of said random disparity block, CHARACTERIZED BY means (312) for counting said binary digits within said zero disparity block and generating a control signal when the bit position is counted; and means (316) responsive to said control signal for inverting all of the digits within one of said segments.
Claim 7
Dependent Claim
104 words
Decoder apparatus (300) for generating a block (200) of n binary digits having random disparity from a block (203) of n binary digits having zero disparity, where n is an even number, and data representing a bit position within said zero disparity block which defines two digit segments (201, 202) each having half the disparity of said random disparity block, CHARACTERIZED BY means (312) for counting said binary digits within said zero disparity block and generating a control signal when the bit position is counted; and means (316) responsive to said control signal for inverting all of the digits within one of said segments.
Claim 8
Dependent Claim
24 words
The apparatus of claim 5 further including means (303) for demultiplexing a serial bitstream comprising said zero disparity block and said bit position data.
Claim 9
Dependent Claim
19 words
The apparatus of claim 6 wherein said bit position data is a series of binary digits having zero disparity.
Claim 10
Dependent Claim
35 words
The apparatus of claim 7 further including translation means (319) for converting said bit position data from a series of binary digits having zero disparity into a conventional series of binary digits having unconstrained disparity.
Claim 11
Dependent Claim
144 words
A digital communications system comprising a coder (100) and decoder (300) wherein said coder converts a first block (200) of n binary digits having random disparity to a second block (203, 204) of n binary digits having zero disparity, where n is an even number, and said decoder converts said second block to said first block, said coder being CHARACTERIZED BY means (103) for determining the disparity of said first block; means (103, 104, 106, 107, 110, 111) for selecting a bit position within said first block which defines two digit segments (201, 202) each having half the disparity of said first block and generating a data representation therefrom; means (115) for inverting all of the digits within a preselected one of said segments; and means (111, 121, 122) for multiplexing said zero disparity block and said data representation into a serial bit stream.
Claim 12
Dependent Claim
144 words
A digital communications system comprising a coder (100) and decoder (300) wherein said coder converts a first block (200) of n binary digits having random disparity to a second block (203, 204) of n binary digits having zero disparity, where n is an even number, and said decoder converts said second block to said first block, said coder being CHARACTERIZED BY means (103) for determining the disparity of said first block; means (103, 104, 106, 107, 110, 111) for selecting a bit position within said first block which defines two digit segments (201, 202) each having half the disparity of said first block and generating a data representation therefrom; means (115) for inverting all of the digits within a preselected one of said segments; and means (111, 121, 122) for multiplexing said zero disparity block and said data representation into a serial bit stream.
Claim 13
Dependent Claim
70 words
The digital communications system of claim 9 wherein said decoder is CHARACTERIZED BY means (303) for demultiplexing said data representation from said serial bit stream; means (311, 312) for counting said binary digits within said zero disparity block and generating a control signal when said bit position is counted; and means (316) responsive to said control signal for inverting all of the digits within said preselected one of said segments.
Claim 14
Dependent Claim
32 words
The digital communications system of claim 10 wherein said data representation of said bit position is a series of binary digits having unconstrained disparity and said counting means is a binary counter.
Claim 15
Dependent Claim
58 words
The digital communications system of claim 11 further including translation table means (119) in said coder for converting said data representation from said series of binary digits having unconstrained disparity to a series having zero disparity format and reciprocal translation table means (309) in the decoder for converting said zero disparity series to said series having unconstrained disparity.
References Cited (Backward Citations)
US2996578A
Cited
US3149323A
Cited
US3300774A
Cited
US3349177A
Cited
US3587086A
Cited
US3502810A
Cited
US3631471A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-01-04 | 1985-07-06 | 1986-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-01-04 | 1989-07-06 | 1990-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-01-04 | 1993-07-06 | 1994-01-05 | $7700.00 | Window Closed / Lapsed |