US3587086A
Expired / Lapsed
US
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Code translator controlled by the most significant digit of a code group
Assignee: International Standard Electric Corp
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Filing: 1967-03-03
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Granted: 1971-06-22
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Expires: 1987-03-03
Abstract
Abstract Logic circuitry operating under control of timing signals increases the average number of ''''1'''' in a code group representing analog amplitudes equal to or higher than 2n 1, where n is equal to the number of digits in a code group, to improve synchronization derived from the ''''1''''s of the code groups received. The condition of the most significant digit is detected; and if it is ''''1,'''' the remainder of the digits are complemented, while if it is ''''0,'''' the remainder of the digits are not changed. In both cases, the condition of the most significant digit is not changed to enable the use of the instant circuitry to recover the original code groups.
Inventors
- 👤 Andre Edouard Joseph Chatelon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:41
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4906; H04L25/4915; H03; H03M; H03M5/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
226 words
A code translator for binary code groups comprising: a first source of binary code groups; an output means; first means coupled to said first source to detect the binary condition of the most significant digit of each code group; second means coupled to said first source, said first means, and said output means to provide at said output means the complement of all the digits of a code group except said most significant digit when said first means detects a binary ''''1'''' condition for said most significant digit; and third means coupled to said first source, said second means, and said output means to provide said most significant digit having said binary ''''1''''condition unchanged at said output means and to provide all the digits of a code group unchanged at said output means when said first means detects a binary ''''0'''' condition for said most significant digit; said first means including a second source providing a plurality of timing signals each time coincident with a different code digit of a code group and an additional signal occurring intermediate adjacent code groups; first coincidence means coupled to said first source and said second source responsive to the timing signal corresponding to said most significant digit; and first bistable means coupled to the output of said first coincidence means and said second source responsive to said additional signal.
Claim 2
Dependent Claim
226 words
A code translator for binary code groups comprising: a first source of binary code groups; an output means; first means coupled to said first source to detect the binary condition of the most significant digit of each code group; second means coupled to said first source, said first means, and said output means to provide at said output means the complement of all the digits of a code group except said most significant digit when said first means detects a binary ''''1'''' condition for said most significant digit; and third means coupled to said first source, said second means, and said output means to provide said most significant digit having said binary ''''1''''condition unchanged at said output means and to provide all the digits of a code group unchanged at said output means when said first means detects a binary ''''0'''' condition for said most significant digit; said first means including a second source providing a plurality of timing signals each time coincident with a different code digit of a code group and an additional signal occurring intermediate adjacent code groups; first coincidence means coupled to said first source and said second source responsive to the timing signal corresponding to said most significant digit; and first bistable means coupled to the output of said first coincidence means and said second source responsive to said additional signal.
Claim 3
Dependent Claim
113 words
A translator according to claim 1, wherein said second means includes second coincidence means coupled to the output of said first bistable means and said second source responsive to the timing signal corresponding to the code dIgit immediately succeeding said most significant digit; second bistable means having two outputs coupled to the output of said second coincidence means and said second source responsive to said additional signal; an inverter means coupled to said first source; and third coincidence means coupled to said inverter means, one of said outputs of said second bistable means and said second source responsive to said timing signals other than said timing signal corresponding to said most significant digit.
Claim 4
Dependent Claim
30 words
A translator according to claim 2, wherein said third means includes fourth coincidence means coupled to said first source and the other of said outputs of said second bistable means.
Claim 5
Dependent Claim
19 words
A translator according to claim 3, wherein said output means is coupled to said third and fourth coincidence means.
Claim 6
Dependent Claim
234 words
A code translator for binary code groups comprising: a first source of binary code groups; an output means; first means coupled to said first source to detect the binary condition of the most significant digit of each code group; second means coupled to said first source, said first means, and said output means to provide at said output means the complement of all the digits of a code group except said most significant digit when said first means detects a binary ''''1'''' condition for said most significant digit; and third means coupled to said first source, said second means, and said output means to provide said most significant digit having said binary ''''1'''' condition unchanged at said output means and to provide all the digits of a code group unchanged at said output means when said first means detects a binary ''''0'''' condition for said most significant digit; said first means including a second source providing n timing signals each coincident with a different one of the n code digits and an additional signal occurring intermediate adjacent code groups; a first AND circuit coupled to said first source and said second source responsive to the timing signal corresponding to said most significant digit; and a first flip-flop having its ''''0'''' input coupled to said second source responsive to said additional signal and its ''''1'''' input coupled to the output of said first AND circuit.
Claim 7
Dependent Claim
234 words
A code translator for binary code groups comprising: a first source of binary code groups; an output means; first means coupled to said first source to detect the binary condition of the most significant digit of each code group; second means coupled to said first source, said first means, and said output means to provide at said output means the complement of all the digits of a code group except said most significant digit when said first means detects a binary ''''1'''' condition for said most significant digit; and third means coupled to said first source, said second means, and said output means to provide said most significant digit having said binary ''''1'''' condition unchanged at said output means and to provide all the digits of a code group unchanged at said output means when said first means detects a binary ''''0'''' condition for said most significant digit; said first means including a second source providing n timing signals each coincident with a different one of the n code digits and an additional signal occurring intermediate adjacent code groups; a first AND circuit coupled to said first source and said second source responsive to the timing signal corresponding to said most significant digit; and a first flip-flop having its ''''0'''' input coupled to said second source responsive to said additional signal and its ''''1'''' input coupled to the output of said first AND circuit.
Claim 8
Dependent Claim
119 words
A translator according to claim 5, wherein said second means includes a second AND circuit coupled to the ''''1'''' output of said first flip-flop and said second source responsive to the timing signal corresponding to the code digit immediately succeeding said most significant digit; a second flip-flop having its ''''0'''' input coupled to said second source responsive to said additional signal and its ''''1'''' input coupled to the output of said second AND circuit; an inverter means coupled to said first source; and a third AND circuit coupled to said inverter means, the ''''1'''' output of said second flip-flop and said second source responsive to said timing signals other than said timing signal corresponding to said most significant digit.
Claim 9
Dependent Claim
28 words
A translator according to claim 6, wherein said third means includes a fourth AND circuit coupled to said first source and the ''''0'''' output of said second flip-flop.
Claim 10
Dependent Claim
22 words
A translator according to claim 7, wherein said output means includes an OR circuit coupled to said third and fourth AND circuits.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-06-21 | 1974-12-21 | 1975-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-06-21 | 1978-12-21 | 1979-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-06-21 | 1982-12-21 | 1983-06-22 | $7700.00 | Window Closed / Lapsed |