Diffused resistor

Claim 2

A resistor, for a semiconductor device, comprising: a semiconductor substrate of a first conductivity type; first and second isolated regions of a second conductivity type, opposite to said first conductivity type, formed on said semiconductor substrate; a first impurity region of the first conductivity type formed in said first isolated region, said first impurity region having first and second end portions and having first and second terminals formed on said first and second end portions, respectively; a second impurity region of the first conductivity type formed in said second isolated region, said second impurity region having third and fourth end portions and having third and fourth terminals formed on said third and fourth end portions, respectively, said third terminal electrically connected only to said second terminal; a fifth terminal formed on said first isolated region; a sixth terminal formed on said second isolated region and electrically connected to said fourth terminal; and means for supplying potentials to said first, fourth and fifth terminals so that depletion layers are generated in said first and second isolated regions, said means for supplying potentials including means for maintaining a substantially constant potential across said first and fifth terminals, said substantially constant potential of a polarity to reverse bias the pn junction.

Claim 3

A resistor, for a semiconductor device, comprising: a semiconductor substrate of a first conductivity type; first and second buried layers of a second conductivity type, opposite to said first conductivity type, formed on said semiconductor substrate; first and second isolated regions of the second conductivity type formed on said semiconductor substrate and on said first and second buried layers, respectively; a first impurity region of the first conductivity type formed in said first isolated region, said first impurity region having first and second end portions and having first and second terminals formed on said first and second end portions, respectively; a second impurity region of the first conductivity type formed in said second isolated region, said second diffused region having third and fourth end portions and having third and fourth terminals formed on said third and fourth end portions, respectively, said third terminal electrically connected only to said second terminal; a fifth terminal formed on said first isolated region; a sixth terminal formed on said second isolated region and electrically connected to said fourth terminal; and means for supplying potentials to said first, fourth and fifth terminals so that depletion layers are generated in said first and second isolated regions, said means for supplying potentials including means for maintaining a substantially constant potential across said first and fifth terminals, said substantially constant potential of a polarity to reverse bias the pn junction.

Claim 4

A resistor, for a semiconductor device, comprising: a semiconductor substrate of a first conductivity type; first and second buried layers of a second conductivity type, opposite to said first conductivity type, formed on said semiconductor substrate; first and second isolated regions of the second conductivity type formed on said semiconductor substrate and on said first and second buried layers, respectively; a first impurity region of the first conductivity type formed in said first isolated region, said first impurity region having first and second end portions and having first and second terminals formed on said first and second end portions, respectively; a second impurity region of the first conductivity type formed in said second isolated region, said second diffused region having third and fourth end portions and having third and fourth terminals formed on said third and fourth end portions, respectively, said third terminal electrically connected only to said second terminal; a fifth terminal formed on said first isolated region; a sixth terminal formed on said second isolated region and electrically connected to said fourth terminal; and means for supplying potentials to said first, fourth and fifth terminals so that depletion layers are generated in said first and second isolated regions, said means for supplying potentials including means for maintaining a substantially constant potential across said first and fifth terminals, said substantially constant potential of a polarity to reverse bias the pn junction.

Claim 5

A resistor according to claim 1 or 2, wherein said first and second isolated regions are each surrounded by an isolating region of the first conductivity type.

Claim 6

A resistor according to claim 1 or 2, wherein each of said first through sixth terminals has a contacting surface, said resistor further comprising an insulating layer formed on said first and second isolated regions and said first and second impurity regions except for the contacting surfaces of said first through sixth terminals.

Claim 7

A resistor according to claim 1 or 2, wherein the first conductivity type is p-type and wherein the potential applied to said first terminal is less positive than the potentials applied to said fourth and fifth terminals.

Claim 8

A resistor according to claim 1 or 2, wherein the first conductivity type is n-type and wherein the potential applied to said first terminal is higher than the potentials applied to said fourth and fifth terminals.

Claim 9

A resistor according to claim 1 or 2, wherein said semiconductor substrate is silicon.

Claim 10

A resistor according to claim 1 or 2, wherein said first and second isolated regions are silicon.

Claim 11

A resistor according to claim 8, wherein each of said silicon first and second isolated regions has a thickness of from 2,000 to 15,000 nm.

Claim 12

A resistor according to claim 2, wherein said first and second buried layers are formed by selectively diffusing donor impurities into the semiconductor substrate.

Claim 13

A resistor according to claim 10, wherein the donor impurities are one of phosphorous, arsenic and antimony.

Claim 14

A resistor according to claim 1 or 2, wherein said first and second impurity regions are formed by diffusing acceptor impurities into said first and second isolated regions.

Claim 15

A resistor according to claim 12, wherein said acceptor impurities are one of boron, indium and aluminum.

Claim 16

A resistor according to claim 1 or 2, wherein said first and second impurity regions have a sheet resistance of from 30 to 5,000 ohm/square.

Claim 17

A resistor according to claim 4, wherein said insulating layer is one of silicon dioxide, silicon nitride and alumina.

Claim 18

A resistor according to claim 15, wherein said insulating layer is a silicon dioxide layer having a thickness of from 200 to 2,000 nm.