Patent US4309224A successfully refreshed from Google Patents.
US4309224A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing a semiconductor device
Assignee: Toshiba Corp
•
Filing: 1979-09-25
•
Granted: 1982-01-05
•
Expires: 1999-09-25
Abstract
Abstract A method for manufacturing a semiconductor device using a polycrystalline silicon layer as an electric conductive portion such as an electrode and/or conductor, which includes steps for doping the polycrystalline silicon layer with an impurity, and applying a radiation beam at least to part of the polycrystalline silicon layer after a heating step, thereby reducing the resistance of the polycrystalline silicon layer thereby to improve the operating speed of the device.
Inventors
- 👤 Tadashi Shibata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 18:11
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10P; H10P32/00; H10P32/30; H10P32/302; H10P34/00; H10P34/40; H10P34/42; Y; Y10; Y10S; Y10S148/00; Y10S148/003; Y10S148/018; Y10S148/02; Y10S148/091; Y10S148/122; Y10S148/123; Y10S438/00; Y10S438/934
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
95 words
A method for manufacturing a semiconductor device comprising the steps of: forming an insulating film on at least part of the surface of a semiconductor substrate; forming an electric conductive portion made of polycrystalline silicon layer doped with at least one impurity, at least on said insulating film; heating said semiconductor substrate to permit at least said electric conductive portion made of said polycrystalline silicon layer to be heated; and applying a radiation beam at least to said electric conductive portion after said heating step, thereby reducing the resistance value of said electric conductive portion.
Claim 2
Independent Claim
95 words
A method for manufacturing a semiconductor device comprising the steps of: forming an insulating film on at least part of the surface of a semiconductor substrate; forming an electric conductive portion made of polycrystalline silicon layer doped with at least one impurity, at least on said insulating film; heating said semiconductor substrate to permit at least said electric conductive portion made of said polycrystalline silicon layer to be heated; and applying a radiation beam at least to said electric conductive portion after said heating step, thereby reducing the resistance value of said electric conductive portion.
Claim 3
Dependent Claim
77 words
A method for manufacturing a semiconductor device according to claim 1, wherein at least said electric conductive portion is covered by at least one insulating film, and at least part of the surface of said at least one insulating film is heated to be melted and reflowed during said heating step, and said radiation beam is applied at least to said electric conductive portion formed of said polycrystalline silicon layer at least through said reflowed insulating film.
Claim 4
Dependent Claim
80 words
A method for manufacturing a semiconductor device according to claim 1, wherein at least said electric conductive portion is covered by at least one insulating film, and a metal layer is also used as an electric conductive portion and is formed on at least the surface of said at least one insulating film, and heated during said heating step before said radiation beam is applied to said polycrystalline electric conductive portion at least through said at least one insulating film.
Claim 5
Dependent Claim
25 words
A method for manufacturing a semiconductor device according to claim 3, wherein said metal layer is an aluminum layer or an aluminum layer containing silicon.
Claim 6
Dependent Claim
41 words
A method for manufacturing a semiconductor device according to claim 1, wherein the at least one impurity with which said polycrystalline silicon layer is doped includes at least one of arsenic, phosphorus, boron, aluminum, germanium, tin, antimony, oxygen, nitrogen, and hydrogen.
Claim 7
Dependent Claim
39 words
A method for manufacturing a semiconductor device according to claim 1, wherein said resistance value of said electric conductive portion is controlled by controlling the beam power of said radiation beam in said step of applying said radiation beam.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-01-04 | 1985-07-06 | 1986-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-01-04 | 1989-07-06 | 1990-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-01-04 | 1993-07-06 | 1994-01-05 | $7700.00 | Window Closed / Lapsed |