Interchangeable magnetic bubble memory

Claim 2

A magnetic bubble memory device comprising: first and second interchangeable memory modules, each of said memory modules including magnetic bubble memory means having at least one major loop, each major loop having a plurality of minor loops where no more than n minor loops are defective and where the defective minor loops are specified by an error map, means for matching said modules such that the operation of each of said interchangeable memory modules are electrically identical, an encoded error map specifying said defective minor loops, and detector means for producing data signals indicating the presence or absence of magnetic bubbles in said minor loops, microprocessor means for providing control signals for controlling the transfer of data signals between said bubble memory means and said microprocessor means; driver means responsive to a control signal from said microprocessor means for transferring said data signals between said bubble memory means and said microprocessor means; and storage means for storing error map instructions for decoding said encoded error map specifying said defective minor loops such that said memory modules are interchangeable regardless of the locations of the defective minor loops in said memory means, and function generator means responsive to enable control signals from said microprocessor means for enabling operation of said device with low average power consumption.

Claim 3

A device as in claim 1 wherein said encoded error map resides within said magnetic memory means.

Claim 4

A device as in claim 1 wherein means for matching compensate for differences in matching of said detector means.

Claim 5

A device as in claim 3 wherein said driver means include transfer driver means responsive to a transfer control signal from said microprocessor means for transferring said data signals between said microprocessor means and said memory means.

Claim 6

A device as in claim 1 wherein said driver means include generate means responsive to a generate control signal from said microprocessor means for generating magnetic bubbles in specified locations in said memory means.

Claim 7

A device as in claim 1 wherein said driver means include replicate means responsive to a replicate control signal from said microprocessor means for dividing a specified one of said bubbles into two bubbles.

Claim 8

A device as in claim 1 wherein said driver means include annihilate means responsive to an annihilate control signal from said microprocessor means for destroying specified ones of said bubbles.

Claim 9

A magnetic bubble memory device comprising: first and second interchangeable memory modules, each of said memory modules including magnetic bubble memory means having at least one major loop, each major loop having a plurality of minor loops where no more than n minor loops are defective and where the defective minor loops are specified by an error map, means for matching said modules such that the operation of each of said interchangeable memory modules are electrically identical, an encoded error map specifying said defective minor loops, and detector means for producing data signals indicating the presence or absence of magnetic bubbles in said minor loops, microprocessor means for providing control signals for controlling the transfer of data signals between said bubble memory means and said microprocessor means; driver means responsive to a control signal from said microprocessor means for transferring said data signals between said bubble memory means and said microprocessor means; and storage means for storing error map instructions for decoding said encoded error map specifying said defective minor loops such that said memory modules are interchangeable regardless of the locations of the defective minor loops in said memory means, function generator means responsive to enable control signals from said microprocessor means for enabling operation of said device with low average power consumption, said detector means including comparator means biased to a first output data signal in the absence of a detected signal, first and second detector elements connected to said comparator means for producing first and second detected signals when a bubble is detecter whereby said comparator means produces a second output data signal.

Claim 10

A magnetic bubble memory device comprising: first and second interchangeable memory modules, each of said memory modules including magnetic bubble memory means having at least one major loop, each major loop having a plurality of minor loops where no more than n minor loops are defective and where the defective minor loops are specified by an error map, means for matching said modules such that the operation of each of said interchangeable memory modules are electrically identical, an encoded error map specifying said defective minor loops, and detector means for producing data signals indicating the presence or absence of magnetic bubbles in said minor loops, microprocessor means for providing control signals for controlling the transfer of data signals between said bubble memory means and said microprocessor means; driver means responsive to a control signal from said microprocessor means for transferring said data signals between said bubble memory means and said microprocessor means; and storage means for storing error map instructions for decoding said encoded error map specifying said defective minor loops such that said memory modules are interchangeable regardless of the locations of the defective minor loops in said memory means, function generator means responsive to enable control signals from said microprocessor means for enabling operation of said device with low average power consumption, said detector means including comparator means biased to a first output data signal in the absence of a detected signal, first and second detector elements connected to said comparator means for producing first and second detected signals when a bubble is detecter whereby said comparator means produces a second output data signal.

Claim 11

A device as in claim 8 wherein said comparator means include first offset means for standardizing said first output signal and second offset means for adjusting said first output signal.

Claim 12

A device as in claim 8 wherein said set of page bits contains 2n+1 bits where n+1 of the bits represent the value of the quality bit.

Claim 13

A device as in claim 10 wherein two adjacent sets of page bits, each encoding a different quality bit, overlap such that n page bits are shared in common by both sets.

Claim 14

A magnetic bubble memory device comprising: first and second interchangeable memory modules, each of said memory modules including magnetic bubble memory means having at least one major loop, each major loop having a plurality of minor loops where no more than n minor loops are defective and where the defective minor loops are specified by an error map, means for matching said modules such that the operation of each of said interchangeable memory modules are electrically identical, an encoded error map specifying said defective minor loops, and detector means for producing data signals indicating the presence or absence of magnetic bubbles in said minor loops, processor means for providing control signals for controlling the transfer of data signals between said bubble memory means and said processor means; driver means responsive to a control signal from said processor means for transferring said data signals between said bubble memory means and said processor means; and storage means for storing error map instructions for decoding said encoded error map specifying said defective minor loops such that said memory modules are interchangeable regardless of the locations of the defective minor loops in said memory means wherein said storage means contains an instruction set for encodation of said error map, said error map read by said processor means and written by said processor means into said memory module by dividing a page into groups, assigning a binary bit value for each page bit, the value dependent upon whether the corresponding minor loop is good or bad, transferring bits for each group containing one or more bad minor loops to a group containing no bad minor loops, assigning a binary bit value to each group containing one or more bad minor loops, and assigning the complementary bit value to each group containing no bad minor loops, the array of said bits thereby forming a quality word for identifying groups containing no bad minor loops, said groups to possibly contain maps of bad loop locations for the associated groups containing bad loops; and encoding each bit of said quality word in another set of page bits such that the value of the encoded bit is unaltered if n bits of said set are altered.

Claim 15

A magnetic bubble memory device comprising: first and second interchangeable memory modules, each of said memory modules including magnetic bubble memory means having at least one major loop, each major loop having a plurality of minor loops where no more than n minor loops are defective and where the defective minor loops are specified by an error map, means for matching said modules such that the operation of each of said interchangeable memory modules are electrically identical, an encoded error map specifying said defective minor loops, and detector means for producing data signals indicating the presence or absence of magnetic bubbles in said minor loops, processor means for providing control signals for controlling the transfer of data signals between said bubble memory means and said processor means; driver means responsive to a control signal from said processor means for transferring said data signals between said bubble memory means and said processor means; and storage means for storing error map instructions for decoding said encoded error map specifying said defective minor loops such that said memory modules are interchangeable regardless of the locations of the defective minor loops in said memory means wherein said storage means contains an instruction set for encodation of said error map, said error map read by said processor means and written by said processor means into said memory module by dividing a page into groups, assigning a binary bit value for each page bit, the value dependent upon whether the corresponding minor loop is good or bad, transferring bits for each group containing one or more bad minor loops to a group containing no bad minor loops, assigning a binary bit value to each group containing one or more bad minor loops, and assigning the complementary bit value to each group containing no bad minor loops, the array of said bits thereby forming a quality word for identifying groups containing no bad minor loops, said groups to possibly contain maps of bad loop locations for the associated groups containing bad loops; and encoding each bit of said quality word in another set of page bits such that the value of the encoded bit is unaltered if n bits of said set are altered.

Claim 16

A device as in claim 12 wherein said set of page bits encoding a quality bit has a majority of bits representing the value of the quality bit.

Claim 17

A device as in claim 12 wherein said processor means reconstitutes the error map from said memory module by reading said sets of page bits which encode the quality word bits from said memory module, decoding said sets to reconstitute the quality word; using the quality word to locate in said memory module the group of maps indentifying the bad loop locations for the page groups containing bad minor loops; and using the quality word and said groups of maps to determine the location and bit values of the error map groups.

Claim 18

A device as in claim 14 wherein said set of page bits encoding a quality bit has a majority of bits representing the value of the quality bit.

Claim 19

A device as in claim 14 wherein said set of page bits contains 2n+1 bits where n+1 of the bits represent the values of the quality bit.

Claim 20

A device as in claim 14 wherein two adjacent sets of page bits, each encoding a different quality bit, overlap such that n page bits are shared in common by both sets.

Claim 21

A portable magnetic bubble memory device comprising: magnetic memory means having at least one major loop, each major loop having a plurality of minor loops where no more than n minor loops are defective, the defective locations specified by an encoded error map for said memory means, detector means connected to said memory means for detecting the presence or absence of magnetic bubbles in said minor loop for generating data signals indicating the presence or absence of said magnetic bubbles, microprocessor means connected to receive said data signals and providing control and enable signals for controlling the transfer of data signals between said memory means and said microprocessor means, said microprocessor means including driver means responsive to said control and enable signals from said microprocessor means for transferring data signals between said memory means and said microprocessor means, storage means for storing error map instructions for enabling the decoding of said encoded error map specifying said defective minor loops such that said error map is decodable regardless of the locations of the defective minor loops in said memory means, and function generator means responsive to said control and enable signals for enabling the transfer of data between said memory means and said microprocessor means thereby enabling operation of said device with low power consumption.

Claim 22

A portable magnetic bubble memory device comprising: magnetic memory means having at least one major loop, each major loop having a plurality of minor loops where no more than n minor loops are defective, the defective locations specified by an encoded error map for said memory means, detector means connected to said memory means for detecting the presence or absence of magnetic bubbles in said minor loop for generating data signals indicating the presence or absence of said magnetic bubbles, microprocessor means connected to receive said data signals and providing control and enable signals for controlling the transfer of data signals between said memory means and said microprocessor means, said microprocessor means including driver means responsive to said control and enable signals from said microprocessor means for transferring data signals between said memory means and said microprocessor means, storage means for storing error map instructions for enabling the decoding of said encoded error map specifying said defective minor loops such that said error map is decodable regardless of the locations of the defective minor loops in said memory means, and function generator means responsive to said control and enable signals for enabling the transfer of data between said memory means and said microprocessor means thereby enabling operation of said device with low power consumption.

Claim 23

An interchangeable magnetic bubble memory device comprising: first and second interchangeable memory modules, each of said modules including first and second magnetic bubble memory means, each of said memory means having at least one major loop where each major loop has a plurality of minor loops where no more than n minor loops are defective, the defective locations specified by an encoded error map for each of said memory means; detector means connected to one of said memory means for detecting magnetic bubbles in said minor loops thereby producing data signals; microprocessor means for providing control signals for controlling the transfer of said data signals between said memory means and said microprocessor means, said microprocessor means including a driver means responsive to a control signal from said microprocessor means for transferring said data signals between said memory means and said processor means; and storage means for storing error map instructions for decoding said encoded error map specifying said defective minor loops such that said memory modules are interchangeable regardless of the locations of the defective minor loops in said memory means wherein said storage means contains an instruction set for encodation of said error map, said error map read by said microprocessor means and written by said microprocessor means into said memory module by dividing a page into groups; assigning a binary bit value for each page bit, the value dependent upon whether the corresponding minor loop is good or bad; transferring bits for each group containing one or more bad minor loops to a group containing no bad minor loops; assigning a binary bit value to each group containing one or more bad minor loops, and assigning the complementary bit value to each group containing no bad minor loops, the array of said bits thereby forming a quality word for identifying groups containing no bad minor loops, said groups to possibly contain maps of bad loop locations for the associated groups containing bad loops; and encoding each bit of said quality word in another set of page bits such that the value of the encoded bit is unaltered if n bits of said set are altered.

Claim 24

An interchangeable magnetic bubble memory device comprising: first and second interchangeable memory modules, each of said modules including first and second magnetic bubble memory means, each of said memory means having at least one major loop where each major loop has a plurality of minor loops where no more than n minor loops are defective, the defective locations specified by an encoded error map for each of said memory means; detector means connected to one of said memory means for detecting magnetic bubbles in said minor loops thereby producing data signals; microprocessor means for providing control signals for controlling the transfer of said data signals between said memory means and said microprocessor means, said microprocessor means including a driver means responsive to a control signal from said microprocessor means for transferring said data signals between said memory means and said processor means; and storage means for storing error map instructions for decoding said encoded error map specifying said defective minor loops such that said memory modules are interchangeable regardless of the locations of the defective minor loops in said memory means wherein said storage means contains an instruction set for encodation of said error map, said error map read by said microprocessor means and written by said microprocessor means into said memory module by dividing a page into groups; assigning a binary bit value for each page bit, the value dependent upon whether the corresponding minor loop is good or bad; transferring bits for each group containing one or more bad minor loops to a group containing no bad minor loops; assigning a binary bit value to each group containing one or more bad minor loops, and assigning the complementary bit value to each group containing no bad minor loops, the array of said bits thereby forming a quality word for identifying groups containing no bad minor loops, said groups to possibly contain maps of bad loop locations for the associated groups containing bad loops; and encoding each bit of said quality word in another set of page bits such that the value of the encoded bit is unaltered if n bits of said set are altered.

Claim 25

A device as in claim 19 wherein said set of page bits encoding a quality bit has a majority of bits representing the value of the quality bit.

Claim 26

A device as in claim 19 wherein said set of page bits contains 2n+1 bits where n+1 of the bits represent the value of the quality bit.

Claim 27

A device as in claim 21 wherein two adjacent sets of page bits, each encoding a different quality bit, overlap such that n page bits are shared in common by both sets.

Claim 28

A device as in claim 19 wherein said microprocessor means reconstitutes the error map from said memory module by reading said sets of page bits which encode the quality word bits from said memory module; decoding said sets to reconstitute the quality word; using the quality word to locate in said memory module the groups of maps identifying the bad loop locations for the page groups containing bad minor loops; and using the quality word and said groups of maps to determine the location and bit values of the error map groups.

Claim 29

A device as in claim 23 wherein said set of page bits encoding a quality bit has a majority of bits representing the value of the quality bit.

Claim 30

A device as in claim 23 wherein said set of page bits contains 2n+1 bits where n+1 of the bits represent the value of the quality bit.

Claim 31

A device as in claim 23 wherein two adjacent sets of page bits, each encoding a different quality bit, overlap such that n page bits are shared in common by both sets.

Claim 32

An interchangeable magnetic bubble memory device comprising: first and second magnetic bubble memory means having at least one non-recirculating track, each track having a plurality of minor loops, where no more than n minor loops are defective where the defective locations are specified by an error map for each of said memory means; detector means connected to one of said memory means producing data signals indicating the presence or absence of magnetic bubbles in said minor loops; microprocessor means providing control signals for controlling the transfer of said data signals between said memory means and said microprocessor means; driver means responsive to a control signal from said microprocessor means for transferring said data signals between said memory means and said microprocessor means; and storage means for storing error map instructions for decoding said encoded error map indicating the n minor loop locations such that said memory means are interchangeable regardless of locations of the defective loops in each of said memory means and function generator means responsive to enable control signals from said microprocessor means for enabling operation of said device with lower average power consumption.

Claim 33

An interchangeable magnetic bubble memory device comprising: first and second magnetic bubble memory means having at least one non-recirculating track, each track having a plurality of minor loops, where no more than n minor loops are defective where the defective locations are specified by an error map for each of said memory means; detector means connected to one of said memory means producing data signals indicating the presence or absence of magnetic bubbles in said minor loops; microprocessor means providing control signals for controlling the transfer of said data signals between said memory means and said microprocessor means; driver means responsive to a control signal from said microprocessor means for transferring said data signals between said memory means and said microprocessor means; and storage means for storing error map instructions for decoding said encoded error map indicating the n minor loop locations such that said memory means are interchangeable regardless of locations of the defective loops in each of said memory means and function generator means responsive to enable control signals from said microprocessor means for enabling operation of said device with lower average power consumption.