US4156934A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Serial bubble memory store
Assignee: AT&T Inc
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Filing: 1977-04-11
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Granted: 1979-05-29
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Expires: 1997-04-11
Abstract
Abstract Disclosed is a bubble memory system adapted for construction on a single construction unit such as a pluggable card and for providing to prospective users a standard interface including an input data port, an output data port, a clear port, a store enable port, read and write enable ports, register select ports and a clock port. In the memory system, a plurality of bubble memory chips are interconnected in parallel with each of the chips being separately accessed for writing or reading purposes with the aid of the register select ports. Common control of the bubble memory chips is obtained through digitally generated control signals. Low voltage protection is provided by appropriately turning off the in-plane rotating field when the power source exhibits a low voltage condition, thereby protecting the stored data.
Inventors
- 👤 Thomas M. Burford
- 👤 George R. Westerman
- 👤 John H. Wuorinen, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:32
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/22; G11; G11C; G11C19/00; G11C19/02; G11C19/08; G11C19/085; G11C19/0875
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
169 words
A bubble memory system adapted for construction on a single building unit and providing an interface indistinguishable to a prospective user from an interface of a nonbubble memory system, including an input data port, an output data port, a clear port, a store enable port, read and write enable ports, register select ports and a clock port comprising: a plurality of bubble memory chips subjected to a common in-plane rotating magnetic field having their input ports connected in parallel and their output ports "collector ORed"; means, responsive to said register select ports, for accessing any one of said bubble memory chips; digital control means responsive to a clock signal applied at said clock port for developing control signals required for proper operation of said bubble memory chips; and means, responsive to the magnitude levels of supply voltages employed in said memory system, for turning off field currents of said bubble memory chips in a specified manner when a low voltage condition is detected in any of said supply voltages.
Claim 2
Dependent Claim
169 words
A bubble memory system adapted for construction on a single building unit and providing an interface indistinguishable to a prospective user from an interface of a nonbubble memory system, including an input data port, an output data port, a clear port, a store enable port, read and write enable ports, register select ports and a clock port comprising: a plurality of bubble memory chips subjected to a common in-plane rotating magnetic field having their input ports connected in parallel and their output ports "collector ORed"; means, responsive to said register select ports, for accessing any one of said bubble memory chips; digital control means responsive to a clock signal applied at said clock port for developing control signals required for proper operation of said bubble memory chips; and means, responsive to the magnitude levels of supply voltages employed in said memory system, for turning off field currents of said bubble memory chips in a specified manner when a low voltage condition is detected in any of said supply voltages.
Claim 3
Dependent Claim
167 words
A memory system responsive to an input data port, a clear port, a store enable port, read and write enable ports, register select ports and a clock port comprising: a plurality of bubble memory chips situated on a pluggable card having their data input ports connected in parallel and their data output ports connected to achieve the Boolean OR function; a controller situated on said pluggable card and responsive to clock signal, for developing digitally timed control signals for affecting common control over said plurality of bubble memory chips; means situated on said pluggable card and responsive to said write and read enable ports for writing into and reading out of any one of said bubble memory chips; and low voltage detection means, situated on said pluggable card and responsive to magnitude levels of supply voltages employed in said memory system, for disabling field currents of said bubble memory chips in a specified manner when a low voltage condition is detected in any of said supply voltages.
Claim 4
Dependent Claim
167 words
A memory system responsive to an input data port, a clear port, a store enable port, read and write enable ports, register select ports and a clock port comprising: a plurality of bubble memory chips situated on a pluggable card having their data input ports connected in parallel and their data output ports connected to achieve the Boolean OR function; a controller situated on said pluggable card and responsive to clock signal, for developing digitally timed control signals for affecting common control over said plurality of bubble memory chips; means situated on said pluggable card and responsive to said write and read enable ports for writing into and reading out of any one of said bubble memory chips; and low voltage detection means, situated on said pluggable card and responsive to magnitude levels of supply voltages employed in said memory system, for disabling field currents of said bubble memory chips in a specified manner when a low voltage condition is detected in any of said supply voltages.
Claim 5
Dependent Claim
57 words
The memory system of claim 2 wherein said controller comprises: memory means responsive to said clock for developing a cyclically advancing sequence of states; digital to analog converter means responsive to said memory means for developing sinusoidal waveforms 90 degrees apart; and logic means for developing cyclic timing signals for controlling said plurality of bubble memory chips.
Claim 6
Dependent Claim
26 words
The controller of claim 3 wherein said memory means is a shift register having one of its outputs fed back through an inverter to its input.
References Cited (Backward Citations)
US3460094A
Cited
US3997877A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-05-28 | 1982-11-27 | 1983-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-05-28 | 1986-11-27 | 1987-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-05-28 | 1990-11-27 | 1991-05-29 | $7700.00 | Window Closed / Lapsed |