Magnetic domain minor loop redundancy system

Claim 2

In a thin magnetic film memory system which includes at least one thin magnetic film capable of supporting magnetic domains responsive to a control means for controllably positioning said magnetic domains in said film from one storage position to another storage position, said film including at least one defective portion such that magnetic domains cannot be positioned therein, a programmable read-only memory for recording the locations of said at least one defective portion, said programmable read-only memory being coupled to said control means for providing signals thereto effective to prevent the use of said defective portions for memory storage.

Claim 3

A thin magnetic film memory system as set forth in claim 1, further including variable delay means coupled to the output of said programmable read-only memory, said variable delay means effective to provide an output signal to said control means responsive to the output from said programmable read-only memory, said output signal effective to inhibit transfer of magnetic domains into or out of portions of said film associated in time with the occurrence of said output signal.

Claim 4

A thin magnetic film memory system as set forth in claim 2, wherein each address location of said programmable read-only memory is effective to store binary data corresponding to the number of storage positions between a first defective storage position and a second defective storage position, the binary data stored at each programmable read-only memory address providing signals effective to control said variable delay means such that said output signal is provided after a predetermined delay which corresponds in time to the number of storage positions between first and second defective positions.

Claim 5

A magnetic domain memory system comprising: a thin magnetic film suitable for use in generating magnetic domains; means disposed on said magnetic film for defining a major path for propagating magnetic domains; and a plurality of minor magnetic domain propagation loops adjacent said path, one or more of said minor loops being inoperable, means for transferring magnetic domains between said minor loops and said major path; and a programmable read-only memory for storing the locations of said one or more inoperable loops, said programmable read-only memory providing output signals effective to inhibit transfer of magnetic domains into or out of said one or more inoperable loops.

Claim 6

A magnetic domain memory system comprising: a thin magnetic film suitable for use in generating magnetic domains; means disposed on said magnetic film for defining a major path for propagating magnetic domains; and a plurality of minor magnetic domain propagation loops adjacent said path, one or more of said minor loops being inoperable, means for transferring magnetic domains between said minor loops and said major path; and a programmable read-only memory for storing the locations of said one or more inoperable loops, said programmable read-only memory providing output signals effective to inhibit transfer of magnetic domains into or out of said one or more inoperable loops.

Claim 7

A magnetic domain memory system including: a plurality of magnetic domain data chips each having a major magnetic domain propagation path means and a plurality of minor loops for propagating magnetic domains, at least one of said minor loops being inoperative for propagating magnetic domains; control means for propagating magnetic domains around each of said major path means and around said loops at a selected clock frequency and controlling transfer of data in the form of magnetic domains between said minor loops and said major path means; a programmable read-only memory connected to said control means for storing the relative location of each defective minor loop on each of said data chips, the output of each address of said programmable read-only memory providing a binary code corresponding to the time delay between defective minor loops; and counter means coupled to the output of said programmable read-only memory, said counter means providing an output pulse, said output pulse being coupled to said control means for inhibiting any read or write operations during the time interval associated with said output pulse, said counter means providing said output pulse responsive to the output of said programmable read-only memory, said output pulse being delayed in time from application of said programmable read-only memory output by a time corresponding to the binary code present at the programmable read-only memory output.

Claim 8

A magnetic domain memory system including: a plurality of magnetic domain data chips each having a major magnetic domain propagation path means and a plurality of minor loops for propagating magnetic domains, at least one of said minor loops being inoperative for propagating magnetic domains; control means for propagating magnetic domains around each of said major path means and around said loops at a selected clock frequency and controlling transfer of data in the form of magnetic domains between said minor loops and said major path means; a programmable read-only memory connected to said control means for storing the relative location of each defective minor loop on each of said data chips, the output of each address of said programmable read-only memory providing a binary code corresponding to the time delay between defective minor loops; and counter means coupled to the output of said programmable read-only memory, said counter means providing an output pulse, said output pulse being coupled to said control means for inhibiting any read or write operations during the time interval associated with said output pulse, said counter means providing said output pulse responsive to the output of said programmable read-only memory, said output pulse being delayed in time from application of said programmable read-only memory output by a time corresponding to the binary code present at the programmable read-only memory output.

Claim 9

A magnetic domain memory system as set forth in claim 5, further including an address counter connected to said programmable read-only memory for sequentially selecting memory locations thereof.

Claim 10

A magnetic domain memory system as set forth in claim 6, further including logic means coupled to the output of said counter means, said logic means operably responsive to said output pulse for providing an inhibit signal to said control means for preventing any read or write operation and for generating a clock signal for said address counter for selecting a new address of said programmable read-only memory and for providing an enable signal to said counter means for enabling transfer of the contents of said new address of said programmable read-only memory into said counter means.

Claim 11

A magnetic domain memory system including: a plurality of magnetic domain memory modules, each module respectively including a plurality of magnetic domain chips; control means associated with each of said chips for propagating magnetic domains, said control means including sensors for detecting the presence or absence of magnetic domains and generators for writing in new magnetic domains, each of said chips including a major magnetic domain propagation path and a plurality of minor loop propagation paths associated therewith, one or more of said minor loops of at least one chip being defective; a programmable read-only memory coupled to said plurality of memory modules and said control means, said programmable read-only memory storing the location of the defective minor loops in each chip; first storage means coupled to said plurality of modules for transferring data in parallel between said plurality of modules and said first storage means; second storage means coupled to an output terminal for transferring data in parallel between said output terminal and said second storage means; said first and second storage means coupled together by serial data transfer means, said first and second storage means further coupled to the output of said programmable read only memory whereby serial data transfer between said first and second storage means is prevented during transfer times corresponding to the location of a defective minor loop.

Claim 12

A magnetic domain memory system including: a plurality of magnetic domain memory modules, each module respectively including a plurality of magnetic domain chips; control means associated with each of said chips for propagating magnetic domains, said control means including sensors for detecting the presence or absence of magnetic domains and generators for writing in new magnetic domains, each of said chips including a major magnetic domain propagation path and a plurality of minor loop propagation paths associated therewith, one or more of said minor loops of at least one chip being defective; a programmable read-only memory coupled to said plurality of memory modules and said control means, said programmable read-only memory storing the location of the defective minor loops in each chip; first storage means coupled to said plurality of modules for transferring data in parallel between said plurality of modules and said first storage means; second storage means coupled to an output terminal for transferring data in parallel between said output terminal and said second storage means; said first and second storage means coupled together by serial data transfer means, said first and second storage means further coupled to the output of said programmable read only memory whereby serial data transfer between said first and second storage means is prevented during transfer times corresponding to the location of a defective minor loop.

Claim 13

A magnetic domain memory system as set forth in claim 8, wherein said first and second storage means respectively comprise parallel to serial shift registers.

Claim 14

A magnetic domain memory system as set forth in claim 8, including counter means connected to the output of said programmable read only memory for providing a signal to said first and second storage means for inhibiting transfer of data therebetween.

Claim 15

A magnetic domain memory system including a thin magnetic film suitable for use in generating magnetic domains, means disposed on said magnetic film for defining a major path for propagating magnetic domains and a plurality of minor magnetic domain propagation loops adjacent said major path, one or more of said minor loops being inoperable, means for transferring magnetic domains between said minor loops and said major path, and a programmable read-only memory having a storage location corresponding to each of said minor loops, programmable read-only memory storage locations associated with operative minor loops containing signals of a first logic level and programmable read-only memory storage locations associated with inoperative minor loops containing signals of a second logic level, a signal of said second logic level being effective to inhibit the transfer of magnetic domains into or out of the minor loop associated therewith.

Claim 16

A magnetic domain memory system including a thin magnetic film suitable for use in generating magnetic domains, means disposed on said magnetic film for defining a major path for propagating magnetic domains and a plurality of minor magnetic domain propagation loops adjacent said major path, one or more of said minor loops being inoperable, means for transferring magnetic domains between said minor loops and said major path, and a programmable read-only memory having a storage location corresponding to each of said minor loops, programmable read-only memory storage locations associated with operative minor loops containing signals of a first logic level and programmable read-only memory storage locations associated with inoperative minor loops containing signals of a second logic level, a signal of said second logic level being effective to inhibit the transfer of magnetic domains into or out of the minor loop associated therewith.