Multiprocessor parcel postage metering system having serial data bus

Claim 2

For controlling the transfer of data between processors in a multiprocessor system, a bus control system including: a system processor operating under the control of a stored program to initiate any data transfer by addressing another processor in the system for a data exchange; a serial data bus common to all of the processors in the system for carrying data to be exchanged between the communicating processors; and attention lines connecting said system processor to each of the other processors in the system, each said attention line connecting said system processor to only one of the other processors in the system, whereby said one of the other processors is conditioned to accept data from said system processor.

Claim 3

A bus control system as defined in claim 1 further including acknowledgment lines connecting each of said other processors to said system processor for permitting an addressed processor to acknowledge receipt of a signal over its attention line from the system processor, said acknowledgment lines being electrically connected to provide a single acknowledgment input signal to said system processor.

Claim 4

A bus control system as recited in claim 2 wherein each of said processors further includes means for generating a ready-to-transmit signal having a first predetermined binary value while data is being shifted onto the serial data bus from the generating processor and a second predetermined value at all other times.

Claim 5

For controlling the transfer of data between processors in a multiprocessor system wherein one of the processors is a system processor, a data control system comprising: attention lines connecting the system processor to each of the remaining processors in the system for enabling the system processor to initiate communications with a selected one of the processors; acknowledgment lines connecting each of the remaining processors to the system processor to enable a selected processor to acknowledge receipt of an attention signal from the system processor; ready lines connecting each of the remaining processors to the system processor for conditioning a selected processor to accept data being transmitted by another selected processor; and a serial data bus common to all of the processors in the system for carrying data between communicating processors.

Claim 6

For controlling the transfer of data between processors in a multiprocessor system wherein one of the processors is a system processor, a data control system comprising: attention lines connecting the system processor to each of the remaining processors in the system for enabling the system processor to initiate communications with a selected one of the processors; acknowledgment lines connecting each of the remaining processors to the system processor to enable a selected processor to acknowledge receipt of an attention signal from the system processor; ready lines connecting each of the remaining processors to the system processor for conditioning a selected processor to accept data being transmitted by another selected processor; and a serial data bus common to all of the processors in the system for carrying data between communicating processors.

Claim 7

A data control system as defined in claim 4 wherein said acknowledgment lines have a common connection to said system processor.

Claim 8

For controlling the transfer of data in a multiprocessor postage metering system including a system processor for a scale subsystem processor for providing scale weight and status data and a postage printing subsystem processor for accepting postage printer setting data and for providing printer status data, wherein each of said processors is capable of being a data transmitting processor or a data receiving processor at a given time, a data control system comprising: attention lines connecting the system processor to the scale subsystem processor and the postage printer subsystem processor for enabling the system processor to initiate communications with a selected one of the subsystem processors by transmission of an attention signal to the selected processor; acknowledgment lines connecting the scale subsystem processor and the postage printer subsystem processor to the system processor to enable a selected one of the subsystem processors to acknowledge receipt of an attention signal from said system processor; ready lines connecting the scale subsystem processor, and the postage printer subsystem processor to the system processor for conditioning a selected processor to accept data transmitted from another selected processor; a serial data bus common to all of the processors in the system for carrying data between communicating processors, said data being segregated into multi-bit words of fixed length; and means for verifying the correct transmission of each data word prior to the transmission of the following data word.

Claim 9

For controlling the transfer of data in a multiprocessor postage metering system including a system processor for a scale subsystem processor for providing scale weight and status data and a postage printing subsystem processor for accepting postage printer setting data and for providing printer status data, wherein each of said processors is capable of being a data transmitting processor or a data receiving processor at a given time, a data control system comprising: attention lines connecting the system processor to the scale subsystem processor and the postage printer subsystem processor for enabling the system processor to initiate communications with a selected one of the subsystem processors by transmission of an attention signal to the selected processor; acknowledgment lines connecting the scale subsystem processor and the postage printer subsystem processor to the system processor to enable a selected one of the subsystem processors to acknowledge receipt of an attention signal from said system processor; ready lines connecting the scale subsystem processor, and the postage printer subsystem processor to the system processor for conditioning a selected processor to accept data transmitted from another selected processor; a serial data bus common to all of the processors in the system for carrying data between communicating processors, said data being segregated into multi-bit words of fixed length; and means for verifying the correct transmission of each data word prior to the transmission of the following data word.

Claim 10

A data control system as defined in claim 6 wherein data is exchanged by serially transmitting data segregated into multi-bit words of fixed length.

Claim 11

A data control system as defined in claim 7 wherein each of said system and subsystem processors further comprise means for verifying the correct transmission of each data word prior to transmission of the following data word, whereby said attention lines and said acknowledgment lines are both disabled to indicate a cessation of data transmission when an error in data transmission occurs.

Claim 12

A data control system as defined in claim 8 wherein said data verifying means comprises means in the data receiving processor for complementing the received data word and for transmitting the complemented data word over the serial data bus to the data transmitting processor and means in the data transmitting processor for comparing the originally transmitted data word with the complemented data word received from the data receiving processor.

Claim 13

A data control system as defined in claim 9 wherein said transmitting processor responds to an error-indicating mismatch between the originally transmitted data word and the returned, complemented data word by terminating its acknowledgment signal when said data receiving processor detects an error in said data transmission.

Claim 14

A data control system as defined in claim 6 further comprising: a peripheral subsystem processor connected to said serial data bus; a plurality of peripheral devices; and a parallel data bus connected between said plurality of peripheral devices and said peripheral subsystem processor such that said peripheral subsystem processor can control in parallel said plurality of peripheral devices.

Claim 15

A data control system as defined in claim 11 wherein one of said plurality of peripheral devices is a document printer.

Claim 16

A data control system as defined in claim 9 wherein said transmitting processor responds to an error-indicating mismatch between the originally transmitted data word and the returned, complemented data word by terminating its attention signal when said data transmitting processor detects an error in said data transmission.

Claim 17

A data control system as defined in claim 8 wherein each of said processors further comprises means for repetitively transmitting a data word when an error in data transmission occurs and wherein said means for verifying the correct transmission of each data word further comprises means for repetitive data word verification.