Patent US4308472A successfully refreshed from Google Patents.
US4308472A
Expired / Lapsed
US
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Clock check circuit
Assignee: AG Communication Systems Corp
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Filing: 1979-12-03
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Granted: 1981-12-29
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Expires: 1999-12-03
Abstract
Abstract An apparatus adapted to check for the continuous presence of an incoming clock pulse train comprising an exclusive OR gate, to the input of which are coupled the clock pulse train and a second train of clock pulses delayed by one half the period of the incoming clock pulse train. A third train of clock pulses delayed by three quarters of the clock period is utilized to strobe the OR gate output into a pair of flip-flops. If the two inputs to the OR gate are the same a fault exists and a flip-flop is set to indicate on which excursion the fault occurred.
Inventors
- 👤 Donald W. McLaughlin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 16:54
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/19
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
228 words
Apparatus for detecting pulse irregularities comprising: a first delay means having an input terminal coupled to a pulse source and an output terminal; said first delay means operated to delay input pulses by one half their period; an exclusive OR means having an output terminal a first input coupled to the pulse source and a second input coupled to said delay means output terminal, whereby an interruption of the incoming pulses produces identical input to said exclusive OR means resulting in an error signal at said output terminal; a second delay means also having an input terminal coupled to a pulse source and an output terminal; said second delay means operated to delay input pulses by three quarters of their period, and a first and a second bistable device each having a set and a clock input and output means; said output terminal of said exclusive OR coupled to the set input of both said first and said second bistable devices; said output terminal of said second delay means coupled to the clock input of said first bistable device, and operated by an error signal at said exclusive OR output terminal to set said first bistable device, whereby said bistable device maintains said operated state indicating said pulse irregularity; and an inverter coupling said second delay means output terminal to the clock input of said second bistable device.
Claim 2
Dependent Claim
228 words
Apparatus for detecting pulse irregularities comprising: a first delay means having an input terminal coupled to a pulse source and an output terminal; said first delay means operated to delay input pulses by one half their period; an exclusive OR means having an output terminal a first input coupled to the pulse source and a second input coupled to said delay means output terminal, whereby an interruption of the incoming pulses produces identical input to said exclusive OR means resulting in an error signal at said output terminal; a second delay means also having an input terminal coupled to a pulse source and an output terminal; said second delay means operated to delay input pulses by three quarters of their period, and a first and a second bistable device each having a set and a clock input and output means; said output terminal of said exclusive OR coupled to the set input of both said first and said second bistable devices; said output terminal of said second delay means coupled to the clock input of said first bistable device, and operated by an error signal at said exclusive OR output terminal to set said first bistable device, whereby said bistable device maintains said operated state indicating said pulse irregularity; and an inverter coupling said second delay means output terminal to the clock input of said second bistable device.
Claim 3
Dependent Claim
87 words
Apparatus as claimed in claim 1, further including a second bistable device having a set input coupled to said exclusive OR output and also a clock input and an output an inverter coupling said second delay means output terminal to the clock input of said second bistable device, said second bistable device operated by an error signal at said exclusive OR output terminal to set said second bistable device during the detection of an irregularity of the opposite polarity of that effective set said first bistable device.
Claim 4
Dependent Claim
35 words
Apparatus as claimed in claim 2, further including latching means operated in response to the setting of either said first or said second bistable devices to latch up and produce a clock failure output indication.
Claim 5
Dependent Claim
19 words
Apparatus as claimed in claim 3, further including reset means operative to reset said bistable devices and said latch.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-12-28 | 1985-06-29 | 1985-12-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-12-28 | 1989-06-29 | 1989-12-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-12-28 | 1993-06-29 | 1993-12-29 | $7700.00 | Window Closed / Lapsed |