Patent US4306246A successfully refreshed from Google Patents.
← Back to Patent Explorer
US4306246A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for trimming active semiconductor devices

Assignee: Motorola Solutions Inc
•
Filing: 1980-06-26
•
Granted: 1981-12-15
•
Expires: 2000-06-26
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method for achieving active devices with closely matched characteristics for use in high performance monolithic integrated circuits. The method comprises providing active devices with appropriately segmented junction regions connected in parallel by their metallic links and severing one or more of the links in order to achieve matching of both the static and dynamic characteristics of two or more active devices.

Inventors

  • 👤 Robert B. Davies
  • 👤 Robert L. Vyne

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 20:21
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H03; H03F; H03F1/00; H03F1/30; H03F1/302; H10D30/00; H10D30/80; H10D30/83; H10D62/133; H10D62/135; H10D62/17; H10D62/213; H10D62/221; H10D62/328; H10D64/00; H10D64/20; H10D64/23; H10D64/231; H10D64/251; H10W; H10W20/00; H10W20/40; H10W20/49

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 76 words
A method for matching field-effect transistors in a monolithic differential amplifier comprising: segmenting the active regions of at least one of the main terminals of at least one of said transistors to provide channel regions of different effective lengths; connecting said segmented regions to a common main terminal by thermally machinable conductive means; monitoring the relative electrical characteristics of said transistors; and thermally machining said conductive means to adjust the relative electrical characteristics of said transistors.
Claim 2
Independent Claim 76 words
A method for matching field-effect transistors in a monolithic differential amplifier comprising: segmenting the active regions of at least one of the main terminals of at least one of said transistors to provide channel regions of different effective lengths; connecting said segmented regions to a common main terminal by thermally machinable conductive means; monitoring the relative electrical characteristics of said transistors; and thermally machining said conductive means to adjust the relative electrical characteristics of said transistors.
Claim 3
Independent Claim 99 words
A method for trimming a field effect transistor in a monolithic integrated circuit which comprises the steps of: forming said field effect transistor with a first segmented junction means coupled to a second junction means through channel regions of different effective lengths to provide a multiplicity of parallel current paths; connecting said first segmented junction means to a common main terminal by a plurality of thermally machinable conductive means; monitoring the electrical characteristics of said field effect transistor; and thermally machining selected ones of said plurality of conductive means to adjust the drain current of said field effect transistor.
Claim 4
Independent Claim 99 words
A method for trimming a field effect transistor in a monolithic integrated circuit which comprises the steps of: forming said field effect transistor with a first segmented junction means coupled to a second junction means through channel regions of different effective lengths to provide a multiplicity of parallel current paths; connecting said first segmented junction means to a common main terminal by a plurality of thermally machinable conductive means; monitoring the electrical characteristics of said field effect transistor; and thermally machining selected ones of said plurality of conductive means to adjust the drain current of said field effect transistor.
Claim 5
Independent Claim 100 words
A method for matching first and second field effect devices in a monolithic differential amplifier comprising: forming first of said devices with a first segmented junction means coupled to a second junction means through channel regions of different effective lengths to provide a multiplicity of parallel current paths; connecting said first segmented junction means to a common main terminal by a plurality of thermally machinable conductive means; monitoring the relative electrical characteristics of said first and second devices; and thermally machining selected ones of said plurality of conductive means to adjust the relative characteristics of said first and second devices.
Claim 6
Independent Claim 100 words
A method for matching first and second field effect devices in a monolithic differential amplifier comprising: forming first of said devices with a first segmented junction means coupled to a second junction means through channel regions of different effective lengths to provide a multiplicity of parallel current paths; connecting said first segmented junction means to a common main terminal by a plurality of thermally machinable conductive means; monitoring the relative electrical characteristics of said first and second devices; and thermally machining selected ones of said plurality of conductive means to adjust the relative characteristics of said first and second devices.
Claim 7
Dependent Claim 13 words
The device of claim 3 where said common main terminal is the drain.
Claim 8
Dependent Claim 14 words
The method of claim 3 where said different effective lengths are 100:1 or greater.
Claim 9
Dependent Claim 29 words
The method of claim 3 where said channel regions of different effective lengths are formed by variable spacing of the first segmented junction means from said second junction means.
Claim 10
Dependent Claim 36 words
The method of claim 3 where said monolithic amplifier comprises thin-film resistor loads for said devices and further including forming conductive means for adjusting at least one of said loads without active trimming of said thin-film.

References Cited (Backward Citations)

US3231810A Cited
US3303400A Cited
US3543102A Cited
US3441804A Cited
US3490040A Cited
US3584183A Cited
US3634924A Cited
US3761787A Cited
US3930304A Cited
US4016483A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1984-12-14 1985-06-15 1985-12-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1988-12-14 1989-06-15 1989-12-15 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1992-12-14 1993-06-15 1993-12-15 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag