Method and apparatus for adjusting transistor current

Claim 3

The method according to claim 1 wherein the step of heating said links comprises applying current of sufficient magnitude thereto to heat such selected links to a temperature above said predetermined melting temperature.

Claim 4

The method according to claim 2 whereby the step of applying said sufficient current through said selected ones of said links comprises the step of discharging a capacitor through each selected link, with the current through a link resulting from such discharge being several orders of magnitude greater than the current carried by such link in normal operation of said transistor.

Claim 5

The combination according to claim 3 wherein said step of discharging a capacitor is effected by touching first and second conductive probes to opposite ends of a selected link, with the first and second probes being connected to opposite ends of said capacitor.

Claim 8

An integrated circuit including in combination: at least one transistor having collector, base, and emitter electrodes, with at least one of the collector and emitter electrodes comprised of at least two segments, one segment having greater area than the other; a conductor having a predetermined minimum width and thickness sufficient to carry operating current for said one electrode; means for connecting said one of said segments having the greater area with said conductor; a conductive fusible link interconnecting said segments, said fusible link having a predetermined melting temperature greater than the temperature attained by such link during normal operation of said transistor; and means at each end of said fusible link for permitting the application thereto of a current having a magnitude sufficient to heat said link to a temperature above said predetermined melting temperature thereby melting said link and severing the interconnection between said segments.

Claim 9

An integrated circuit including in combination: at least one transistor having collector, base, and emitter electrodes, with at least one of the collector and emitter electrodes comprised of at least two segments, one segment having greater area than the other; a conductor having a predetermined minimum width and thickness sufficient to carry operating current for said one electrode; means for connecting said one of said segments having the greater area with said conductor; a conductive fusible link interconnecting said segments, said fusible link having a predetermined melting temperature greater than the temperature attained by such link during normal operation of said transistor; and means at each end of said fusible link for permitting the application thereto of a current having a magnitude sufficient to heat said link to a temperature above said predetermined melting temperature thereby melting said link and severing the interconnection between said segments.

Claim 10

A monolithic integrated circuit having a P substrate including in combination: at least one lateral PNP transistor having collector, base and emitter electrodes, with an N base diffusion in said P substrate, said collector electrode comprised of at least two segments; A conductor having a predetermined minimum width and thickness sufficient to carry operating current for said collector electrode; means for connecting one of said segments with said conductor; a conductive fusible link interconnecting said segments of said collector, said fusible link having a predetermined melting temperature greater than the temperature obtained by said link during normal operation of said transistor; and means at each end of said fusible link for permitting the application thereto of a current having a magnitude sufficient to heat said link to a temperature above said predetermined melting temperature, thereby melting said link and severing the interconnection between said segments, the relative sizes of said segments determining the percentage of total current conducted by said collector.

Claim 11

A monolithic integrated circuit having a P substrate including in combination: at least one lateral PNP transistor having collector, base and emitter electrodes, with an N base diffusion in said P substrate, said collector electrode comprised of at least two segments; A conductor having a predetermined minimum width and thickness sufficient to carry operating current for said collector electrode; means for connecting one of said segments with said conductor; a conductive fusible link interconnecting said segments of said collector, said fusible link having a predetermined melting temperature greater than the temperature obtained by said link during normal operation of said transistor; and means at each end of said fusible link for permitting the application thereto of a current having a magnitude sufficient to heat said link to a temperature above said predetermined melting temperature, thereby melting said link and severing the interconnection between said segments, the relative sizes of said segments determining the percentage of total current conducted by said collector.

Claim 12

The combination according to claim 1 wherein said collector electrode is a generally circular electrode with a first one of said segments occupying the greater part of said circle and a second one of said segments occupying a lesser part, said conductor being connected with the first segment and the fusible link interconnecting the first and second segments, the fusible link and conductor being integrally formed of the same material, with the width of the fusible link being less than the width of said conductor.

Claim 13

A monolithic integrated circuit operational amplifier permitting current offset adjustment including in combination: first and second separate current paths having conductors and having a predetermined differential current offset therebetween in the absence of any input signals to said operational amplifier; first and second transistors each having collector, base, and emitter electrodes, with the emitter-collector paths thereof connected respectively in series in said first and second current paths, at least one of the collector and emitter electrodes of each of said first and second transistors being comprised of at least two segments with one of the segments of each such segmented electrode being connected to the corresponding separate conductor for said first and second current paths; fusible conductive means having a predetermined melting temperature for connecting the other segment of each of such segmented electrodes in each of said transistors with said one segment; and means for permitting the selective application of a current to said fusible conductive means of sufficient magnitude to heat said fusible conductive means to a temperature in excess of said predetermined temperature thereby breaking the connection between said segments.

Claim 14

A monolithic integrated circuit operational amplifier permitting current offset adjustment including in combination: first and second separate current paths having conductors and having a predetermined differential current offset therebetween in the absence of any input signals to said operational amplifier; first and second transistors each having collector, base, and emitter electrodes, with the emitter-collector paths thereof connected respectively in series in said first and second current paths, at least one of the collector and emitter electrodes of each of said first and second transistors being comprised of at least two segments with one of the segments of each such segmented electrode being connected to the corresponding separate conductor for said first and second current paths; fusible conductive means having a predetermined melting temperature for connecting the other segment of each of such segmented electrodes in each of said transistors with said one segment; and means for permitting the selective application of a current to said fusible conductive means of sufficient magnitude to heat said fusible conductive means to a temperature in excess of said predetermined temperature thereby breaking the connection between said segments.

Claim 15

The combination according to claim 9 wherein said first and second transistors comprise lateral PNP current source transistors for supplying currents having a predetermined offset, and said electrode having said segments comprises the collector of each of said first and second transistors.

Claim 16

The combination according to claim 10 wherein each of said lateral PNP transistors includes a segmented circular collector electrode substantially surrounding an emitter electrode, with said one of said segments constituting the greater part of the circle occupied by said collector electrode and said other of said segments constituting a lesser part of the circle.