Patent US4305124A successfully refreshed from Google Patents.
US4305124A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pipelined computer
Assignee: NCR Voyix Corp
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Filing: 1979-09-26
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Granted: 1981-12-08
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Expires: 1999-09-26
Abstract
Abstract A pipelined computer which executes high level language instructions is disclosed. The pipelined computer includes a memory for storing the high level language instructions therein. A plurality of microprogrammed digital computers are coupled in parallel to the memory, and are also intercoupled via an interlocking bus. The microprogrammed computers, in conjunction with the interlocking bus, form a pipeline for executing the high level language instructions. Each of the computers is a separately microprogrammable stage of the pipeline.
Inventors
- 👤 Daniel J. Marro
- 👤 David B. Schuck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:12
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3867
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
330 words
In a pipelined computer, having a memory means for storing programs of high level language instructions and a plurality of microprogrammed digital computer means wherein each one of said plurality of microprogrammed digital computer means forms a stage of said pipelined computer, said pipelined computer having n-stages, and wherein each of said plurality of microprogrammed digital computer means is coupled to said memory means, an interlocking bus, comprising: (n-1) buffer means, each one of said buffer means coupled between consecutive ones of said plurality of microprogrammed digital computer means for providing a predetermined level of buffering therebetween, said buffer means also comprising; (a) a register means for holding a quantum of data therein, said register means having an input terminal adapted to receive said quantum of data and having an output terminal adapted to transmit said quantum of data, wherein said input terminal is operatively connected to one of said plurality of microprogrammed digital computer means and said output terminal is operatively connected to the next consecutive stage of said plurality of microprogrammed digital computer means; and (b) synchronizing means, operatively connected between the same consecutive stages of said microprogrammed digital computer means as said register means, and further operatively connected to said register means, said consecutive stages of said plurality of microprogrammed digital computer means being an i th -stage and an (i+1)-stage, said synchronizing means having a first and second output terminal for transmitting a halt control signal, said first output terminal operatively connected to the i th -stage of said microprogrammed digital computer means and said second output terminal operatively connected to the (i+1)-stage of said microprogrammed digital computer means, said synchronizing means cooperating with said register means, for halting said (i+1)-stage of said microprogrammed digital computer means when attempting to read said register means if said register means is empty or for halting said i th -stage of said microprogrammed digital computer means when attempting to load said register means if said register means is full.
Claim 2
Dependent Claim
330 words
In a pipelined computer, having a memory means for storing programs of high level language instructions and a plurality of microprogrammed digital computer means wherein each one of said plurality of microprogrammed digital computer means forms a stage of said pipelined computer, said pipelined computer having n-stages, and wherein each of said plurality of microprogrammed digital computer means is coupled to said memory means, an interlocking bus, comprising: (n-1) buffer means, each one of said buffer means coupled between consecutive ones of said plurality of microprogrammed digital computer means for providing a predetermined level of buffering therebetween, said buffer means also comprising; (a) a register means for holding a quantum of data therein, said register means having an input terminal adapted to receive said quantum of data and having an output terminal adapted to transmit said quantum of data, wherein said input terminal is operatively connected to one of said plurality of microprogrammed digital computer means and said output terminal is operatively connected to the next consecutive stage of said plurality of microprogrammed digital computer means; and (b) synchronizing means, operatively connected between the same consecutive stages of said microprogrammed digital computer means as said register means, and further operatively connected to said register means, said consecutive stages of said plurality of microprogrammed digital computer means being an i th -stage and an (i+1)-stage, said synchronizing means having a first and second output terminal for transmitting a halt control signal, said first output terminal operatively connected to the i th -stage of said microprogrammed digital computer means and said second output terminal operatively connected to the (i+1)-stage of said microprogrammed digital computer means, said synchronizing means cooperating with said register means, for halting said (i+1)-stage of said microprogrammed digital computer means when attempting to read said register means if said register means is empty or for halting said i th -stage of said microprogrammed digital computer means when attempting to load said register means if said register means is full.
Claim 3
Dependent Claim
30 words
An interlocking bus, according to claim 1, further comprising at least one register means for transmitting said quantum of data to a non-consecutive stage of said microprogrammed digital computer means.
Claim 4
Dependent Claim
16 words
An interlocking bus, according to claim 2, wherein said register means comprises a triggerable D-type register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-12-07 | 1985-06-08 | 1985-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-12-07 | 1989-06-08 | 1989-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-12-07 | 1993-06-08 | 1993-12-08 | $7700.00 | Window Closed / Lapsed |