One's complement adder

Claim 2

An adder for adding binary signals representing two binary numbers A i , B i in the one's complement notation each of the numbers having i bits, where i is an integer other than zero, comprising: two sets of input terminals adapted to have applied to them binary signals representing A i B i ; a carry-in terminal adapted to have a binary signal representing a binary number to be summed with the two lowest order bits of A i B i ; i output resultant terminals, said adder including means for producing binary resultant signals F i representing the sum of A i , B i , and the signal applied to the carry-in terminal at the i output resultant terminals; a generate output signal terminal, said adder including means for producing a binary signal representing a binary carry generate number G, the value of which is independent of any signal applied to the carry-in terminal, and for applying the carry generate signal G to the generate output terminal; and circuit means for applying the carry generate signal G to the carry-in terminal of the adder.

Claim 3

The adder of claim 1 in which i equals 5.

Claim 4

An adder for adding binary signals representing two binary numbers A i , B i in the one's complement notation, each of the numbers having i bits where i is an integer other than zero, comprising: two sets of input terminals adapted to have applied to them the signals representing A i and B i ; a carry-in terminal adapted to have a binary signal representing a binary number to be summed with the lowest order bits of A i and B i ; i output resultant terminals; said adder including means for producing binary resultant signals F i representing the sum of A i , B i and the signal applied to the carry-in terminal at the i output resultant terminals; a carry generate output signal terminal, said adder including means for producing a binary carry generate signal G which is a function of only A i and B i , and for applying the carry generate signal G to the generate output signal terminal; and circuit means for applying the carry generate signal G to the carry-in terminal of the adder.

Claim 5

An adder for adding binary signals representing two binary numbers A i , B i in the one's complement notation, each of the numbers having i bits where i is an integer other than zero, comprising: two sets of input terminals adapted to have applied to them the signals representing A i and B i ; a carry-in terminal adapted to have a binary signal representing a binary number to be summed with the lowest order bits of A i and B i ; i output resultant terminals; said adder including means for producing binary resultant signals F i representing the sum of A i , B i and the signal applied to the carry-in terminal at the i output resultant terminals; a carry generate output signal terminal, said adder including means for producing a binary carry generate signal G which is a function of only A i and B i , and for applying the carry generate signal G to the generate output signal terminal; and circuit means for applying the carry generate signal G to the carry-in terminal of the adder.

Claim 6

The adder of claim 3 in which i equals 5.

Claim 7

An adder for adding binary signals representing two binary numbers A i an B i in the one's complement notation where i=5, whereby A i has five bits A16, A8, A4, A2 and A1 and B i has five bits B16, B8, B2 and B1; said adder having means for producing carry generate signals G16, G8, G4, G2 and G1 and half sum signals HS16, HS8, HS4, HS2 comprising: two sets of input terminals of five terminals each adapted to have applied to them the signals representing A i and B i respectively; a carry-in terminal adapted to have a binary signal representing a binary digit to be summed with bits A1 and B1; five output resultant terminals, said adder including means for producing binary resultant signals F i representing the binary sum of A i plus B i plus the digit applied to the carry-in terminal, and for applying the resultant signals F i to the output resultant terminals; a carry generate output signal terminal, said adder including means for producing a carry generate binary signal G which is determined by the Boolean algabraic equation: G=G16+HS16.G8+HS16.HS8.G4+HS16.HS8.HS4.G2+HS16.HS8.HS4.HS2.G1 and for applying G to said generate output signal; and circuit means for applying G to the carry-in terminal of the adder.

Claim 8

An adder for adding binary signals representing two binary numbers A i an B i in the one's complement notation where i=5, whereby A i has five bits A16, A8, A4, A2 and A1 and B i has five bits B16, B8, B2 and B1; said adder having means for producing carry generate signals G16, G8, G4, G2 and G1 and half sum signals HS16, HS8, HS4, HS2 comprising: two sets of input terminals of five terminals each adapted to have applied to them the signals representing A i and B i respectively; a carry-in terminal adapted to have a binary signal representing a binary digit to be summed with bits A1 and B1; five output resultant terminals, said adder including means for producing binary resultant signals F i representing the binary sum of A i plus B i plus the digit applied to the carry-in terminal, and for applying the resultant signals F i to the output resultant terminals; a carry generate output signal terminal, said adder including means for producing a carry generate binary signal G which is determined by the Boolean algabraic equation: G=G16+HS16.G8+HS16.HS8.G4+HS16.HS8.HS4.G2+HS16.HS8.HS4.HS2.G1 and for applying G to said generate output signal; and circuit means for applying G to the carry-in terminal of the adder.