Current mode 5-bit arithmetic logic unit with parity

Claim 2

A current mode 5-bit arithmetic logic unit for performing a repertoire of arithmetic and logic operations on two 5-bit bytes and for generating a plurality of intermediate-level output signals, said 5-bit arithmetic logic unit comprising: a first portion for receiving said first and second 5-bit bytes Ai and Bi, a carry-in signal CIN, and a mode control signal, said first portion generating a 5-bit binary output resultant signal Fi in response to said mode control signal, said first portion further generating a plurality of intermediate-level signals, a propogate signal P, a generate signal G, and a carry-out signal COUT; and a second portion responsive to said intermediate-level signals, and further responsive to said carry-in signal CIN and a carry-in duplicate signal CIND, said second portion generating output signals comprising a parity of the carries signal PC, a parity of the half-sum signal HS, a parity of the half-parities signal HP, and a carry error signal CE.

Claim 3

The current mode 5-bit arithmetic logic unit recited in claim 1 wherein said mode control signal received by said first portion is a 5-bit binary signal M16 M8 M4 M2 M1, wherein said intermediate-level signals generated by said first portion comprise parity of the half-sum intermediate signals HSi, parity of the half-parities intermediate signals HPi, carry propagate intermediate signals Pi, parity propagate intermediate signals PPi, carry generate intermediate signals Gi, and parity generate intermediate signals GPi, where i=1, 2, 4, 8, 16, and wherein said second portion generates said output signals in accordance with the following tables: Parity and Error Outputs: HS = HS1 ⊕ HS2 ⊕ HS4 ⊕ HS8 ⊕ HS16 hp = hp1 ⊕ hp2 ⊕ hp4 ⊕ hp8 ⊕ hp16 pc = m16.{[cin(hs1 + hs2.hs4 + hs2.hs8)] ⊕ [g1.(hs2 + hs4.hs8)] ⊕ [g2.(hs4 + hs8)] ⊕ [g4.hs8] ⊕ [g8]} ce = [cind + cin] m16 ______________________________________ half Sum, Half Parity, Carry Propagate, Parity Propagate, Carry Generate, and Parity Generate Intermediate Signals (HSi, HPi, Pi, PPi, Gi, GPi): Gi = M8 · Ai · Bi + M4 · Ai · Bi GPi = M8 · Bi · Ai + M1 · Bi · Ai Pi = Ai + M2 · Bi PPi = Bi + M2 · Ai + M4 · Ai HSi = Gi · Pi HPi = GPi · PPi M8 M4 M2 M1 HSi HPi ______________________________________ 0 0 0 0 Ai Bi 0 0 0 1 A i + Bi Ai · Bi 0 0 1 0 Ai + Bi Ai + Bi 0 0 1 1 1 Ai -⊕ Bi 0 1 0 0 Ai · Bi Ai + Bi 0 1 0 1 Bi Ai 0 1 1 0 Ai -⊕ Bi 1 0 1 1 1 Ai + Bi Ai + Bi 1 0 0 0 Ai · Bi Ai · Bi 1 0 0 1 Ai ⊕ Bi 0 1 0 1 0 Bi Ai 1 0 1 1 Ai + Bi Ai · Bi 1 1 0 0 0 Ai ⊕ Bi 1 1 0 1 Ai · Bi Ai · Bi 1 1 1 0 Ai · Bi Ai + Bi. 1 1 1 1 Ai Bi ______________________________________