US3649817A
Expired / Lapsed
US
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Arithmetic and logical unit with error checking
Assignee: International Business Machines Corp
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Filing: 1970-07-29
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Granted: 1972-03-14
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Expires: 1990-07-29
Abstract
Abstract In an arithmetic and logical unit suitable for ''''Adding,'''' ''''AND,'''' ''''OR'''' and ''''Exclusive OR'''' operations, additions are performed to the carry-dependent sum formation principle, while during the execution of logical operations, operand bit parity functions related to the respective operation are generated by means of a function generator. In an operation-dependent checking circuit the carries of additions or the parity functions of logical operations are combined for result parity prediction independently of the sum formed. For error-checking the result, the parity of the result bits is compared for compliance with the predicted parity.
Inventors
- 👤 Gunter Keller
- 👤 Guenter Knauft
- 👤 Petar Skuin
- 👤 Edwin Vogt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:22
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
138 words
An arithmetic and logical unit for performing ''''Adding,'''' ''''AND,'''' ''''OR'''' and ''''Exclusive-OR'''' operations with carrydependent sum formation for the purpose of error-checking the carry and sum bits by parity prediction by means of ExclusiveORing of the operand and carry parities and by comparing the predicted with the actual result parity, comprising: a source of operation control signals for selecting logical operations; a function generator circuit operatively connected to said source which, as a function of said operation control signals, produces a bit parity function related to the respective operation; a source of operand parity signals; a checking circuit comprising means for Exclusive-ORing said operand parity with said parity function, independently of the result of the logical operation to be executed, to generate the predicted parity; and comparison means for comparing said predicted parity to the actual result parity.
Claim 2
Dependent Claim
138 words
An arithmetic and logical unit for performing ''''Adding,'''' ''''AND,'''' ''''OR'''' and ''''Exclusive-OR'''' operations with carrydependent sum formation for the purpose of error-checking the carry and sum bits by parity prediction by means of ExclusiveORing of the operand and carry parities and by comparing the predicted with the actual result parity, comprising: a source of operation control signals for selecting logical operations; a function generator circuit operatively connected to said source which, as a function of said operation control signals, produces a bit parity function related to the respective operation; a source of operand parity signals; a checking circuit comprising means for Exclusive-ORing said operand parity with said parity function, independently of the result of the logical operation to be executed, to generate the predicted parity; and comparison means for comparing said predicted parity to the actual result parity.
Claim 3
Dependent Claim
183 words
An arithmetic and logical unit in accordance with claim 1 further comprising: means within said function generator for generating result bits in accordance with the selected logical operation; means within said function generator for generating carries during an addition operation; means for providing the operand parity of each input operand; a first group of Exclusive-OR circuits which form the result parity of the generated result bits; at least one second group of Exclusive-OR circuits which, as a function of operation control signals, form the parity of the processeD carries during addition and the parity of the parity functions of the individual positions during the execution of a logical operation; a first individual Exclusive-OR circuit for combining the operand parities; and a second individual Exclusive-OR circuit for combining the output signal of the second group of Exclusive-OR circuits with the output signal of the first individual Exclusive-OR circuit to form the predicted parity; the output of the second individual Exclusive-OR circuit being connected to said comparison means, the second input of which is formed by the output of the first group of Exclusive-OR circuits.
Claim 4
Dependent Claim
27 words
An arithmetic and logical unit in accordance with claim 2 further including means for inverting one of the operand parities provided to said first individual Exclusive-OR circuit.
Claim 5
Dependent Claim
60 words
An arithmetic and logical unit in accordance with claim 3, wherein the function generator circuit comprises means for generating at an output the logical OR of the input operands when the operation control signals specify the ''''AND'''' operation and for generating at an output the logical AND of the input operands when the operation control signals specify the ''''OR'''' operation.
Claim 6
Dependent Claim
72 words
An arithmetic and logical unit in accordance with claim 4, wherein: there is provided a logical combine circuit which derives AND and OR bit functions from the operand bits; and the function generator circuit comprises gate circuits, to the input of each of which is applied one of said bit functions, and the output of each of which, depending upon the respective operation control signal, is selectively connected to said checking circuit.
Claim 7
Dependent Claim
97 words
An arithmetic and logical unit in accordance with claim 5, wherein at least some of the output lines of the logical combine circuit are connected to a carry generator and a sum function generator circuit which, in a predetermined manner, form a carry in accordance with the relationship (An. Bn) v (An. Cn-1) v (Bn. Cn-1) and a sum function in accordance with the relationship (An v n v Cn-1) . (An v Bn v Cn-1), where An and Bn are the operand bits of the respective position and Cn-1 is a carry accruing to that position.
Claim 8
Dependent Claim
82 words
An arithmetic and logical unit in accordance with claim 6, wherein the carry generator receives the carry of more than one adjoining lower position together with the OR functions of the logical combine circuits of such positions, and the carry generator forms the carry in accordance with the relationship Cn An . Bn v (An v Bn) . Cn-1 v(An-1 v Bn-1 ) . (An v Bn) . Cn-2 V(An-2 v Bn-2) . (An-1 v Bn-1) . (An v Bn) . Cn-3
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-03-14 | 1975-09-13 | 1976-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-03-14 | 1979-09-13 | 1980-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-03-14 | 1983-09-13 | 1984-03-14 | $7700.00 | Window Closed / Lapsed |