US3555255A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Error detection arrangement for data processing register
Assignee: AT&T Inc
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Filing: 1968-08-09
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Granted: 1971-01-12
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Expires: 1988-08-09
Abstract
Abstract Outputs of the ordered stages of a register are applied to a first-ZERO-detecting logic and outputs of the latter are used to predict what parity state should prevail in registered information after a predetermined operation has been performed on the registered information. Illustrative predetermined operations are high speed counting and marking a low order bit of a predetermined type. The first-ZERO-detecting logic is actuated simultaneously with the initiation of the operation to be performed on the registered information and is utilized in the performance of that operation. Predicted parity is then compared with a parity indication computed after the operation has been completed to evaluate the accuracy with which the operation was carried out.
Inventors
- 👤 Wing N Toy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 19:13
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/28
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
143 words
In combination: a multistage register containing data having a predetermined information-dependent characteristic, said stages having predetermined different orders of data significance and each having at least two data information-representative states of operation; logic circuits coupled to said register stages, said logic circuits including means for interconnecting such circuits to one another so that the logic circuit coupled to the lowest order stage which is in a predetermined data state inhibits actuation of all higher order logic circuits; means, including said logic circuits, for performing a predetermined operation on said data; means simultaneously operable with said performing means for indicating whether or not said characteristic is to be changed by said operation; means coupled to said register for determining a post-operation indication of said characteristic; and means comparing outputs of said indicating means and said determining means for evaluating the accuracy of said operation.
Claim 2
Dependent Claim
143 words
In combination: a multistage register containing data having a predetermined information-dependent characteristic, said stages having predetermined different orders of data significance and each having at least two data information-representative states of operation; logic circuits coupled to said register stages, said logic circuits including means for interconnecting such circuits to one another so that the logic circuit coupled to the lowest order stage which is in a predetermined data state inhibits actuation of all higher order logic circuits; means, including said logic circuits, for performing a predetermined operation on said data; means simultaneously operable with said performing means for indicating whether or not said characteristic is to be changed by said operation; means coupled to said register for determining a post-operation indication of said characteristic; and means comparing outputs of said indicating means and said determining means for evaluating the accuracy of said operation.
Claim 3
Dependent Claim
29 words
The combination in accordance wIth claim 1 in which said performing means comprises an additional register, and means transferring to said additional register the contents of the first-mentioned register.
Claim 4
Dependent Claim
41 words
The combination in accordance with claim 2 in which said performing means further comprises means coupling outputs of said logic circuits to said additional register, and means actuating said lowest order logic circuit to alter the information value of said data.
Claim 5
Dependent Claim
47 words
The combination in accordance with claim 3 in which said coupling means includes means coupling said lowest order logic to alter a part of said data transferred from the stage of said first-mentioned register coupled to said lowest order logic and from all lower order stages thereof.
Claim 6
Dependent Claim
26 words
The combination in accordance with claim 3 in which said actuating means comprises means coupling outputs of said additional register to inputs of the first-mentioned register.
Claim 7
Dependent Claim
61 words
The combination in accordance with claim 1 in which said performing means comprises an additional register, means resetting said additional register, means coupling outputs of said logic circuits to said additional register for setting one stage thereof, and means coupling outputs of said additional register to inputs of the first-mentioned register for setting a stage thereof corresponding to said one stage.
Claim 8
Dependent Claim
28 words
The combination in accordance with claim 1 in which said performing means comprises means actuating said lowest order logic circuit to alter the information value of said data.
Claim 9
Dependent Claim
37 words
The combination in accordance with claim 7 in which said performing means comprises means coupling an output of each of said logic circuits to inputs of its coupled register stage and of all lower order register stages.
Claim 10
Dependent Claim
55 words
The combination in accordance with claim 7 in which said performing means comprises an output gate in each of said logic circuits for operation in response to said actuating means, and means coupling an output of each logic circuit output gate to an input connection of the output gate of each lower order logic circuit.
Claim 11
Dependent Claim
62 words
The combination in accordance with claim 7 in which said indicating means comprises a multistable circuit, means setting said multistable circuit to a first or a second condition of stable operation to represent a first or a second condition of said data information characteristic, and means altering the state of said multistable circuit in response to predetermined outputs of said logic circuits.
Claim 12
Dependent Claim
38 words
The combination in accordance with claim 10 in which said multistable circuit is bistable, and said altering means complements said bistable circuit in response to actuation of an odd numbered one of said logic circuits in said order.
Claim 13
Dependent Claim
36 words
The combination in accordance with claim 10 in which said altering means comprises means operative in response to actuation of any of said logic circuits in said order for changing the state of said multistable circuit.
Claim 14
Dependent Claim
78 words
The combination in accordance with claim 7 in which said change indicating means comprises: means responsive to an output of said lowest order logic circuit for producing signals indicating whether an odd or an even number of said stages contain data to be altered by said operation; and means comparing said signals from said producing means and a preoperation output of said determining means to indicate whether or not said characteristic is to be changed by said operation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-01-11 | 1974-07-13 | 1975-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-01-11 | 1978-07-13 | 1979-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-01-11 | 1982-07-13 | 1983-01-12 | $7700.00 | Window Closed / Lapsed |