US3758760A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Error detection for arithmetic and logical unit modules
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1972-04-07
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Granted: 1973-09-11
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Expires: 1992-04-07
Abstract
Abstract A modular error detector for an adder of the type which provides both arithmetic and logical functions and incorporates carrylook-ahead addition is described. The error detector includes parity prediction of logical and arithmetic terms together with partial duplication. Error checking of four bit arithmetic/logic modules is integrated with error checking of the carry-look-ahead unit. Also, check parity generation and testing of the operands is integrated with the parity prediction.
Inventors
- 👤 J Cowan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:14
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F7/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
203 words
In an adder having a plurality of arithmetic/logic units responsive to a pair of four bit operands, a set of function selection signals and a carry-in signal, for selectively generating arithmetic and logical functions, including carrylook-ahead signals; a carry-look-ahead unit, responsive to said carry-look-ahead signals, for generating carry signals; error detecting logic including: A. elementary logic forming the AND, OR and exclusive OR functions of respective bit pairs, each bit being from one of the input operands; B. AND prediction logic means, responsive to said elementary functions, for generating an AND function parity signal; C. exclusive OR prediction logic means, responsive to said elementary functions, for generating an exclusive OR function parity signal; D. check bit generating means, responsive to said prediction logic means and the function selection signals, for generating a parity check bit; E. operand checking means, responsive to said exclusive OR prediction means and input operand check bits, for detecting erroneous transfer in of the input operands; G. duplicating carry-look-ahead logic means, responsive to said elementary functions, for generating carry-look-ahead signals; H. carry error detecting means, responsive to said duplicate carry-look-ahead signals, the arithmetic logic unit''s carry-out signal, and a carry-look-ahead unit''s output, for detection of errors in these units.
Claim 2
Dependent Claim
203 words
In an adder having a plurality of arithmetic/logic units responsive to a pair of four bit operands, a set of function selection signals and a carry-in signal, for selectively generating arithmetic and logical functions, including carrylook-ahead signals; a carry-look-ahead unit, responsive to said carry-look-ahead signals, for generating carry signals; error detecting logic including: A. elementary logic forming the AND, OR and exclusive OR functions of respective bit pairs, each bit being from one of the input operands; B. AND prediction logic means, responsive to said elementary functions, for generating an AND function parity signal; C. exclusive OR prediction logic means, responsive to said elementary functions, for generating an exclusive OR function parity signal; D. check bit generating means, responsive to said prediction logic means and the function selection signals, for generating a parity check bit; E. operand checking means, responsive to said exclusive OR prediction means and input operand check bits, for detecting erroneous transfer in of the input operands; G. duplicating carry-look-ahead logic means, responsive to said elementary functions, for generating carry-look-ahead signals; H. carry error detecting means, responsive to said duplicate carry-look-ahead signals, the arithmetic logic unit''s carry-out signal, and a carry-look-ahead unit''s output, for detection of errors in these units.
Claim 3
Dependent Claim
26 words
The error detecting logic of claim 1, further comprising: I. grouping said Error detecting logic into portions for processing pairs of four bits of the operands.
Claim 4
Dependent Claim
29 words
The error detecting logic of claim 2, further comprising: J. a single integrated circuit for realizing a multiple of the grouped logic of pairs of four bits of operands.
Claim 5
Dependent Claim
64 words
The adder of claim 1, further comprising: I. primary elementary logic forming the AND, OR and exclusive OR functions of respective four bit pairs; J. adder logic means, responsive to said primary elementary logic, for selectively generating arithmetic sums and logical functions of the input pairs; K. carry-look-ahead logic, responsive to said primary elementary logic, for providing carry, carry propagate and carry generate signals.
Claim 6
Dependent Claim
48 words
The adder of claim 4, further comprising: L. a plurality of arithmetic and logical units realized in respective integrated circuits; M. a plurality of carry-look-ahead integrated circuits; N. a plurality of error detecting logic integrated circuits, responsive to respective said arithmetic and logical units and said carry-look-ahead logic.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-10 | 1977-03-12 | 1977-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-10 | 1981-03-12 | 1981-09-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-10 | 1985-03-12 | 1985-09-11 | $7700.00 | Window Closed / Lapsed |