Patent US4291241A successfully refreshed from Google Patents.
US4291241A
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Timing signal generating circuit
Assignee: Hitachi Ltd
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Filing: 1979-02-16
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Granted: 1981-09-22
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Expires: 1999-02-16
Abstract
Abstract A timing signal generating circuit including a clock source which generates clock pulses of a predetermined period, a binary counter which divides the frequency of the clock pulses from the clock source by n, a logical array which decodes an output of the binary counter and which is composed of semiconductor elements and flip-flop circuits which are set or reset by outputs of the logical array in response to the clock pulses from the clock source with the outputs of the flip-flop circuits being used as timing signals.
Inventors
- 👤 Koichi Mayama
- 👤 Noboru Yamaguchi
- 👤 Mamoru Sugie
- 👤 Yuzo Kita
- 👤 Shigeru Yoshizawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 11:11
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G06; G06F; G06F1/00; G06F1/04; G11C19/00; G11C19/02; G11C19/08; G11C19/0875; H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/1506; H03K5/15066
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
114 words
A timing signal generating circuit comprising clock source means for generating basic clock pulses of a predetermined period, binary counter means for counting the number of clock pulses from said clock source means and for providing the count value as a binary code output, means forming a logical array for decoding the output of said binary counter means and providing outputs, said logical array means including semiconductor elements arrayed in the form of a matrix, and flip-flop means for being set and reset in response to outputs of said logical array means at the timing of the clock pulses applied thereto from said clock source means and providing outputs for utilization as timing signals.
Claim 2
Dependent Claim
114 words
A timing signal generating circuit comprising clock source means for generating basic clock pulses of a predetermined period, binary counter means for counting the number of clock pulses from said clock source means and for providing the count value as a binary code output, means forming a logical array for decoding the output of said binary counter means and providing outputs, said logical array means including semiconductor elements arrayed in the form of a matrix, and flip-flop means for being set and reset in response to outputs of said logical array means at the timing of the clock pulses applied thereto from said clock source means and providing outputs for utilization as timing signals.
Claim 3
Dependent Claim
15 words
A timing signal generating circuit according to claim 1, wherein said semiconductor elements are diodes.
Claim 4
Dependent Claim
16 words
A timing signal generating circuit according to claim 1, wherein said semiconductor elements are MOS transistors.
Claim 5
Dependent Claim
19 words
A timing signal generating circuit according to claim 1, 2 or 3 wherein said flip-flop means comprise J-K flip-flops.
Claim 6
Dependent Claim
147 words
A timing signal generating circuit comprising clock source means for generating clock pulses of a predetermined period, first binary counter means for counting the number of the clock pulses from said clock source means and providing the count value as a binary code output and a carry-out signal, input means for applying a predetermined control signal, second binary counter means for counting the number of the pulses corresponding to the carry-out signal of said first binary counter means and the control signal from said input means and providing the count value as a binary code output, means forming a logical array for decoding the outputs of said first and second binary counter means, and flip-flop means for being set and reset by outputs of said logical array means in response to the clock pulses from said clock source means and providing outputs for utilization as timing signals.
Claim 7
Dependent Claim
147 words
A timing signal generating circuit comprising clock source means for generating clock pulses of a predetermined period, first binary counter means for counting the number of the clock pulses from said clock source means and providing the count value as a binary code output and a carry-out signal, input means for applying a predetermined control signal, second binary counter means for counting the number of the pulses corresponding to the carry-out signal of said first binary counter means and the control signal from said input means and providing the count value as a binary code output, means forming a logical array for decoding the outputs of said first and second binary counter means, and flip-flop means for being set and reset by outputs of said logical array means in response to the clock pulses from said clock source means and providing outputs for utilization as timing signals.
Claim 8
Dependent Claim
66 words
A timing signal generating circuit according to claim 5, wherein said input means comprises means forming another logical array for decoding the output of said second binary counter means, and providing an output means for applying a control command, and gate means for providing said control signal in response to said control command from said applying means and an output of said another logical array means.
Claim 9
Dependent Claim
172 words
A timing signal generating circuit comprising clock source means for generating basic clock pulses of a predetermined period, binary counter means for counting the number of the clock pulses from said clock source means and for providing the count value as a binary code output, means forming a logical array for decoding the output of said binary counter means and providing outputs, said logical array means including semiconductor elements arrayed in the form of a matrix, and flip-flop means for being set and reset by outputs of said logical array means in response to the clock pulses from said clock source means and providing outputs for utilization as timing signals, further comprising input means for applying predetermined input signals, another flip-flop means for storing the input signals from said input means in response to the clock signals from said clock source means and a timing signal corresponding to the zero output of said binary counter means, and AND gate means for taking the logical products between outputs of said another flip-flop means.
Claim 10
Dependent Claim
172 words
A timing signal generating circuit comprising clock source means for generating basic clock pulses of a predetermined period, binary counter means for counting the number of the clock pulses from said clock source means and for providing the count value as a binary code output, means forming a logical array for decoding the output of said binary counter means and providing outputs, said logical array means including semiconductor elements arrayed in the form of a matrix, and flip-flop means for being set and reset by outputs of said logical array means in response to the clock pulses from said clock source means and providing outputs for utilization as timing signals, further comprising input means for applying predetermined input signals, another flip-flop means for storing the input signals from said input means in response to the clock signals from said clock source means and a timing signal corresponding to the zero output of said binary counter means, and AND gate means for taking the logical products between outputs of said another flip-flop means.
Claim 11
Dependent Claim
40 words
A timing signal generating circuit according to claim 1, 2 or 3, further including delay means for delaying the clock pulses from said clock source means, said flip-flop means being set and reset in response to the delayed clock pulses.
Claim 12
Dependent Claim
16 words
A timing signal generating circuit according to claim 8, wherein said flip-flop means comprise R-S flip-flops.
Claim 13
Dependent Claim
144 words
A timing signal generating circuit comprising clock source means for generating basic clock pulses of a predetermined period, binary counter means for counting the number of the clock pulses from said clock source means and for providing the count value as a binary code output, means forming a logical array for decoding the output of said binary counter means and providing outputs, said logical array means including semiconductor elements arrayed in the form of a matrix, and flip-flop means for being set and reset by outputs of said logical array means in response to the clock pulses from said clock source means and providing outputs for utilization as timing signals, said flip-flop means being arranged for receiving the clock pulses from said clock source means for being set and reset by the outputs of said logical array means in response to the clock pulses.
Claim 14
Dependent Claim
144 words
A timing signal generating circuit comprising clock source means for generating basic clock pulses of a predetermined period, binary counter means for counting the number of the clock pulses from said clock source means and for providing the count value as a binary code output, means forming a logical array for decoding the output of said binary counter means and providing outputs, said logical array means including semiconductor elements arrayed in the form of a matrix, and flip-flop means for being set and reset by outputs of said logical array means in response to the clock pulses from said clock source means and providing outputs for utilization as timing signals, said flip-flop means being arranged for receiving the clock pulses from said clock source means for being set and reset by the outputs of said logical array means in response to the clock pulses.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-09-21 | 1985-03-23 | 1985-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-09-21 | 1989-03-23 | 1989-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-09-21 | 1993-03-23 | 1993-09-22 | $7700.00 | Window Closed / Lapsed |