Patent US4290185A successfully refreshed from Google Patents.
US4290185A
Expired / Lapsed
US
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Method of making an extremely low current load device for integrated circuit
Assignee: STMicroelectronics lnc USA
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Filing: 1979-05-29
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Granted: 1981-09-22
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Expires: 1999-05-29
Abstract
Abstract A MOSFET random access memory having an extremely low current load memory cell is disclosed. The memory cell comprises a cross-coupled binary stage in which one or more paths to ground can be selectively switched on or off through true and complement data nodes. Impedance means connect a power supply node to the data nodes for charging the data nodes to predetermined voltage levels. The impedance means comprise an intrinsic-extrinsic junction of a substantially pure, intrinsic semiconductor material and a diffusion of extrinsic conductivity impurities disposed within a region of the intrinsic semiconductor material. The impedance means is formed by an isoplanar silicon gate process as an integral portion of a polycrystalline silicon strip which interconnects the power supply node to a data node. A portion of the polycrystalline silicon strip is extended from the data node to form the gate of the transistor to which it is cross-coupled.
Inventors
- 👤 Vernon G. McKenny
- 👤 Tsiu C. Chan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 08:46
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; H10B; H10B10/00; H10B10/15; H10P; H10P14/00; H10P14/40; H10P14/416; H10P32/00; H10P32/30; H10P32/302; H10W; H10W20/00; H10W20/40
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
320 words
A method for producing an integrated circuit of the type including an insulated gate field effect transistor and a load impedance device for conducting current from a power supply node through the channel of the transistor comprising: providing a semiconductor substrate chip of a first conductivity type; growing a layer of thermal oxide on the surface of the substrate; depositing a layer of nitride on the oxide layer; forming a mask over the combined nitride and oxide layers and photoresisting to define an active area and a field area; removing the layer of nitride from the field area; implanting ion impurities of the first conductivity type in the field area; removing the photoresist from the active area; growing a layer of thermal oxide over the field area; removing the nitride and oxide layers over the active area; growing a layer of gate oxide over the active area; depositing a layer of undoped semiconductor material over the gate oxide; masking and photoresisting the undoped semiconductor layer to define a gate strip having a gate interconnect portion; depositing a diffusion-impervious layer over the undoped gate interconnect portion; masking and photoresisting the diffusion-impervious layer to define the situs of a potential extremely low current load impedance device; removing the oxide layer from the active area to define the situs of drain and source regions; diffusing impurities of the opposite conductivity type into the unmasked portions of the undoped semiconductor layer and into the active area, whereby a diffused gate and diffused source and drain regions are formed by the diffusion of impurities into gate strip and into the active area of the substrate on either side of the gate strip, a nondiffused channel region being defined in the active area beneath the gate oxide and gate strip, and an intrinsic-extrinsic junction being formed in the gate interconnect at the interface of the undoped semiconductor material beneath the mask with the adjacent impurity diffusion.
Claim 2
Independent Claim
320 words
A method for producing an integrated circuit of the type including an insulated gate field effect transistor and a load impedance device for conducting current from a power supply node through the channel of the transistor comprising: providing a semiconductor substrate chip of a first conductivity type; growing a layer of thermal oxide on the surface of the substrate; depositing a layer of nitride on the oxide layer; forming a mask over the combined nitride and oxide layers and photoresisting to define an active area and a field area; removing the layer of nitride from the field area; implanting ion impurities of the first conductivity type in the field area; removing the photoresist from the active area; growing a layer of thermal oxide over the field area; removing the nitride and oxide layers over the active area; growing a layer of gate oxide over the active area; depositing a layer of undoped semiconductor material over the gate oxide; masking and photoresisting the undoped semiconductor layer to define a gate strip having a gate interconnect portion; depositing a diffusion-impervious layer over the undoped gate interconnect portion; masking and photoresisting the diffusion-impervious layer to define the situs of a potential extremely low current load impedance device; removing the oxide layer from the active area to define the situs of drain and source regions; diffusing impurities of the opposite conductivity type into the unmasked portions of the undoped semiconductor layer and into the active area, whereby a diffused gate and diffused source and drain regions are formed by the diffusion of impurities into gate strip and into the active area of the substrate on either side of the gate strip, a nondiffused channel region being defined in the active area beneath the gate oxide and gate strip, and an intrinsic-extrinsic junction being formed in the gate interconnect at the interface of the undoped semiconductor material beneath the mask with the adjacent impurity diffusion.
Claim 3
Dependent Claim
42 words
The method as defined in claim 1 including the step: depositing an insulating oxide layer over the chip area; masking and photoresisting the insulating oxide layer to define the location of conductive interconnects; forming conductive metallization deposits at the conductive interconnect locations.
Claim 4
Dependent Claim
62 words
The method as defined in claim 1 including the step of removing the mask from the situs of the impedance device and diffusing a relatively light dose of impurities through the undoped semiconductor material, the intrinsic-extrinsic junction being transformed into an extrinsic-extrinsic junction characterized by a heavy concentration of impurities disposed in junction forming relation with a relatively light concentration of impurities.
Claim 5
Dependent Claim
47 words
The method as defined in claim 1 including the step of forming an electrical union of the gate interconnect portion with the common power supply node by electrically connecting the undoped portion of the intrinsic-extrinsic junction of the load impedance device directly to the power supply node.
Claim 6
Dependent Claim
77 words
The method as defined in claim 1 wherein first and second diffused extrinsic regions are formed on both sides of an intermediate interior undoped region of the interconnect portion and including the step of forming an electrical union of the gate interconnect portion with the common power supply node by electrically connecting the first diffused extrinsic region directly to the power supply node and electrically connecting the second diffused extrinsic region to the channel of the transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-09-21 | 1985-03-23 | 1985-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-09-21 | 1989-03-23 | 1989-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-09-21 | 1993-03-23 | 1993-09-22 | $7700.00 | Window Closed / Lapsed |