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US4283641A
Expired / Lapsed
US
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Feedback biasing circuit arrangement for transistor amplifier
Assignee: Plessey Overseas Ltd
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Filing: 1978-10-20
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Granted: 1981-08-11
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Expires: 1998-10-20
Abstract
Abstract A circuit suitable for providing constant current bias for I.C's includes two transistors arranged to pass current in parallel in which base emitter voltage applied to one transistor is derived from the base emitter voltage applied to the other transistor with the base emitter voltage applied to the one transistor reduced by a component proportional to the magnitude of the current passed by the other transistor.
Inventors
- 👤 John A. Skingley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 10:55
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/34; H03F3/343; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/30; H03F1/00; H03F1/30; H03F1/302; H03F3/347; H03F3/45; H03F3/45071; H03F3/45479; H10; H10D; H10D84/00; H10D84/60; H10D84/611; H10D84/613; H10D84/615
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
176 words
An amplifier circuit arrangement, comprising: first and second transistors, each having a base, an emitter and a collector electrode, the first and second transistors being connected to pass current in parallel with one another; interconnecting means for interconnecting the first and second transistors so that a base-emitter voltage applied to the first transistor is derived from a base-emitter voltage applied to the second transistor; biasing reduction means connected between the base and collector of said second transistor for reducing the base-emitter voltage applied to the first transistor by a component proportional to the magnitude of the current passed by the second transistor; and an amplifier transistor having a base input for receiving a signal frequency to be amplified, an emitter; and a collector output for delivering amplified output signals, the collector output of the amplifier transistor being connected to said second transistor so as to pass current in series with the said second transistor, the collector of the said first transistor being connected to the base of said amplifier transistor for providing base bias current thereto.
Claim 2
Dependent Claim
176 words
An amplifier circuit arrangement, comprising: first and second transistors, each having a base, an emitter and a collector electrode, the first and second transistors being connected to pass current in parallel with one another; interconnecting means for interconnecting the first and second transistors so that a base-emitter voltage applied to the first transistor is derived from a base-emitter voltage applied to the second transistor; biasing reduction means connected between the base and collector of said second transistor for reducing the base-emitter voltage applied to the first transistor by a component proportional to the magnitude of the current passed by the second transistor; and an amplifier transistor having a base input for receiving a signal frequency to be amplified, an emitter; and a collector output for delivering amplified output signals, the collector output of the amplifier transistor being connected to said second transistor so as to pass current in series with the said second transistor, the collector of the said first transistor being connected to the base of said amplifier transistor for providing base bias current thereto.
Claim 3
Dependent Claim
45 words
A circuit arrangement as claimed in claim 1, wherein the biasing reduction means comprises a resistor connected such that the potential drop across the resistor is subtracted from the base-emitter voltage of the second transistor to provide the base-emitter voltage applied to the first transistor.
Claim 4
Dependent Claim
22 words
A circuit arrangement as claimed in any one of claims 1 and 2, wherein said circuit arrangement comprises a monolithic integrated circuit.
Claim 5
Dependent Claim
204 words
An amplifier circuit arrangement, comprising: first and second transistors, each having a base, an emitter and a collector electrode, the first and second transistors being connected to pass current in parallel with one another; interconnecting means for interconnecting the first and second transistors so that a base-emitter voltage applied to the first transistor is derived from a base-emitter voltage applied to the second transistor; biasing reduction means for reducing the base-emitter voltage applied to the first transistor by a component proportional to the magnitude of the current passed by the second transistor; and an amplifier transistor having a base input, an emitter, and a collector output, the amplifier transistor being connected to said second transistor so as to pass current in series with said second transistor, the collector of said first transistor being connected to the base of said amplifier transistor for providing base bias current thereto; said circuit arrangement further comprising decoupling means connected between the collector of the said first transistor and the base input of the amplifier transistor for decoupling the collector of the said first transistor to signal frequencies handled by the said amplifier transistor in order to reduce substantially signal feed-back to the base of the said amplifier transistor.
Claim 6
Dependent Claim
204 words
An amplifier circuit arrangement, comprising: first and second transistors, each having a base, an emitter and a collector electrode, the first and second transistors being connected to pass current in parallel with one another; interconnecting means for interconnecting the first and second transistors so that a base-emitter voltage applied to the first transistor is derived from a base-emitter voltage applied to the second transistor; biasing reduction means for reducing the base-emitter voltage applied to the first transistor by a component proportional to the magnitude of the current passed by the second transistor; and an amplifier transistor having a base input, an emitter, and a collector output, the amplifier transistor being connected to said second transistor so as to pass current in series with said second transistor, the collector of said first transistor being connected to the base of said amplifier transistor for providing base bias current thereto; said circuit arrangement further comprising decoupling means connected between the collector of the said first transistor and the base input of the amplifier transistor for decoupling the collector of the said first transistor to signal frequencies handled by the said amplifier transistor in order to reduce substantially signal feed-back to the base of the said amplifier transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-08-10 | 1985-02-09 | 1985-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-08-10 | 1989-02-09 | 1989-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-08-10 | 1993-02-09 | 1993-08-11 | $7700.00 | Window Closed / Lapsed |