Input protection device for insulated gate field effect transistor

Claim 2

An overvoltage protection circuit for the input of a field effect device to be protected, comprising: a pair of insulated gate transistors consisting of an N channel transistor and a P channel transistor, each transistor of the pair having a conduction path and a gate electrode; a source of operating potential; the N channel transistor connected to the source of operating potential; the P channel transistor connected to the input of the device to be protected; the conduction paths of each of the transistors connected in series between the source of operating potential and the input to the device to be protected; and means connecting the gate electrodes of each of the transistors to each other.

Claim 3

The input protection circuit of claim 1, wherein: the N channel transistor has a drain region and a source region of a first conductivity type with an intervening channel region therebetween of a second conductivity type; and the P channel transistor has a drain region and a source region of the second conductivity type with an intervening channel region of the first conductivity type.

Claim 4

The input protection circuit of claim 2, wherein: the source region of the N channel transistor is connected to the source of operating potential; the drain region of the N channel transistor is connected to the source region of the P channel transistor; and the drain region of the P channel transistor is connected to the input of the device to be protected.

Claim 5

An overvoltage protection circuit for the input of a field effect device to be protected, comprising: first and second pairs of insulated gate transistors each pair consisting of an N channel transistor and a P channel transistor, each transistor of each pair having a conduction path and a gate electrode; a source of positive operating potential; the N channel transistor of the first pair of transistors connected to the source of positive potential; the P channel transistor of the first pair of transistors connected to the input of the device to be protected; a source of negative operating potential; the conduction path of the first pair of insulated gate transistors connected in series between the source of positive potential and the input to the device to be protected; means connecting the gate electrodes of the first pair of insulated gate field effect transistors to each other; the N channel transistor of the second pair of transistors connected to the input of the device to be protected; the P channel transistor of the second pair of transistors connected to the source of negative potential; the conduction path of the second pair of insulated gate transistors connected in series between the input of the device to be protected and the source of negative potential; and means connecting the gate electrodes of the second pair of insulated gate transistors to each other.

Claim 6

An overvoltage protection circuit for the input of a field effect device to be protected, comprising: first and second pairs of insulated gate transistors each pair consisting of an N channel transistor and a P channel transistor, each transistor of each pair having a conduction path and a gate electrode; a source of positive operating potential; the N channel transistor of the first pair of transistors connected to the source of positive potential; the P channel transistor of the first pair of transistors connected to the input of the device to be protected; a source of negative operating potential; the conduction path of the first pair of insulated gate transistors connected in series between the source of positive potential and the input to the device to be protected; means connecting the gate electrodes of the first pair of insulated gate field effect transistors to each other; the N channel transistor of the second pair of transistors connected to the input of the device to be protected; the P channel transistor of the second pair of transistors connected to the source of negative potential; the conduction path of the second pair of insulated gate transistors connected in series between the input of the device to be protected and the source of negative potential; and means connecting the gate electrodes of the second pair of insulated gate transistors to each other.

Claim 7

The input protection circuit of claim 4, wherein: each N channel transistor of each pair of insulated gate transistors has a drain region and a source region of a first conductivity type with an intervening channel region therebetween of a second conductivity type; and each P channel transistor of each pair of insulated gate transistors has a drain region and a source region of the second conductivity type with an intervening channel region of the first conductivity type.

Claim 8

The input protection circuit of claim 5, wherein: the source region of the N channel transistor of the first pair of transistors is connected to the source of positive potential; the drain region of the N channel transistor of the first pair of insulated gate transistors is connected to the source region of the P channel transistor of the first pair of insulated gate transistors; the drain region of the P channel transistor of the first pair of insulated gate transistors is connected to the input of the device to be protected; the souce region of the N channel transistor of the second pair of insulated gate transistors is connected to the input of the device to be protected; the drain region of the N channel transistor of the second pair of insulated gate transistors is connected to the source region of the P channel insulated gate transistor of the second pair of transistors; and the drain region of the P channel transistor of the second pair of insulated gate transistors is connected to the source of negative potential.