US4282489A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Metastable detector
Assignee: Harris Corp
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Filing: 1979-05-14
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Granted: 1981-08-04
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Expires: 1999-05-14
Abstract
Abstract A metastable arbiter circuit for determining the state of a monitored flip-flop contains an additional flip-flop that is provided on the same semiconductor chip as the operating flip-flop, the metastable condition of which is to be monitored. This additional flip-flop is hardwired in the SET state, so that its high and low outputs can be referenced to indicate when a defined state condition has been achieved in the operating flip-flop. The Q and Q outputs of the second flip-flop from which a pair of reference voltages are derived are applied to a pair of comparators, one comparator being used for negative referencing, the other for positive referencing. Through this circuit combination, there is achieved both level detection and hysteresis to produce a high true output when the complementary outputs of the operating flip-flop have reached a defined stable state.
Inventors
- 👤 William T. DeRienzo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 10:40
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/165; G01R19/16533; G01R19/16557; H; H03; H03K; H03K5/00; H03K5/22; H03K5/24
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
106 words
A circuit arrangement for detecting the metastable condition of a flip-flop comprising: first means for supplying a set of reference voltages respectively related to prescribed state conditions of said flip-flop; and second means, coupled to said first means and to said flip-flop, for comparing the respective Q and Q outputs of said flip-flop with said set of reference voltages and generating a first prescribed logical output during the period of time that said flip-flop is in a metastable condition and thereafter generating a second prescribed logical output upon the termination of said metastable condition and the return of said flip-flop to one of its bistable conditions.
Claim 2
Dependent Claim
106 words
A circuit arrangement for detecting the metastable condition of a flip-flop comprising: first means for supplying a set of reference voltages respectively related to prescribed state conditions of said flip-flop; and second means, coupled to said first means and to said flip-flop, for comparing the respective Q and Q outputs of said flip-flop with said set of reference voltages and generating a first prescribed logical output during the period of time that said flip-flop is in a metastable condition and thereafter generating a second prescribed logical output upon the termination of said metastable condition and the return of said flip-flop to one of its bistable conditions.
Claim 3
Dependent Claim
35 words
A circuit arrangement according to claim 1, wherein said first means comprises a further flip-flop having a prescribed stable state, from the Q and Q outputs of which said set of reference voltages is derived.
Claim 4
Dependent Claim
51 words
A circuit arrangement according to claim 1, wherein said second means comprises a plurality of comparators coupled to compare individual respective ones of said reference voltages with the Q and Q outputs of said flip-flop and to thereby produce outputs from which said first and second prescribed logical outputs are derived.
Claim 5
Dependent Claim
16 words
A circuit arrangement according to claim 3, wherein each of said comparators is a hysteresis comparator.
Claim 6
Dependent Claim
78 words
A circuit arrangement according to claim 3, wherein said second means comprises a first comparator for comparing the Q output of said flip-flop with one of said reference voltages and generating a preselected logic output upon said Q output exceeding said one reference voltage, and a second comparator for comparing the Q output of said flip-flop with the other of said reference voltages and generating said preselected logic output upon said other reference voltage exceeding said Q output.
Claim 7
Dependent Claim
78 words
A circuit arrangement according to claim 3, wherein said second means comprises a first comparator for comparing the Q output of said flip-flop with one of said reference voltages and generating a preselected logic output upon said one reference voltage exceeding said Q output, and a second comparator for comparing the Q output of said flip-flop with the other of said reference voltages and generating said preselected logic output upon said Q output exceeding said other reference voltage.
Claim 8
Dependent Claim
82 words
A circuit arrangement according to claim 5, wherein said second means further comprises a third comparator for comparing the Q output of said flip-flop with the other of said references voltages and generating said preselected logic output upon said Q output exceeding said other of said reference voltages, and a fourth comparator for comparing the Q output of said flip-flop with said one of said reference voltages and generating said preselected logic output upon said one reference voltage exceeding said Q output.
Claim 9
Dependent Claim
35 words
A circuit arrangement according to claim 5, wherein said first means comprises a further flip-flop having a prescribed stable state, from the Q and Q outputs of which said set of reference voltages is derived.
Claim 10
Dependent Claim
35 words
A circuit arrangement according to claim 6, wherein said first means comprises a further flip-flop having a prescribed stable state, from the Q and Q outputs of which said set of reference voltages is derived.
Claim 11
Dependent Claim
35 words
A circuit arrangement according to claim 7, wherein said first means comprises a further flip-flop having a pescribed stable state, from the Q and Q outputs of which said set of reference voltages is derived.
Claim 12
Dependent Claim
19 words
A circuit arrangement according to claim 2, wherein each of said flip-flops is formed in the same semiconductor chip.
Claim 13
Dependent Claim
42 words
A circuit arrangement according to claim 2, wherein said first means further comprises a pair of voltage dividers coupled to the Q and Q outputs of said further flip-flop, said set of reference voltages being supplied by way of said voltage dividers.
Claim 14
Dependent Claim
42 words
A circuit arrangement according to claim 8, wherein said first means further comprises a pair of voltage dividers coupled to the Q and Q outputs of said further flip-flop, said set of reference voltages being supplied by way of said voltage dividers.
Claim 15
Dependent Claim
42 words
A circuit arrangement according to claim 9, wherein said first means further comprises a pair of voltage dividers coupled to the Q and Q outputs of said further flip-flop, said set of reference voltages being supplied by way of said voltage dividers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-08-03 | 1985-02-02 | 1985-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-08-03 | 1989-02-02 | 1989-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-08-03 | 1993-02-02 | 1993-08-04 | $7700.00 | Window Closed / Lapsed |