Self-checking flip-flop

Claim 2

In a flip-flop circuit which includes a bistable device connected to be responsive to set input, reset input and clock input signals for changing state in dependence upon set and/or reset signals at the time of a falling clock, the combination comprising: first and second latching circuits each having set and reset states and being connected to be placed in the set state, individually and respectively in response to different combinations of the set and reset input signals as applied to the bistable device, and further connected to be placed in the reset state on the falling clock in synchronism therewith; and means connected to the first and second latching circuits to provide an indication of concurrence of the set state of the first and second latching circuits.

Claim 3

In a flip-flop circuit as set forth in claim 1, including first means connected to the first latching circuit for providing thereto a first signal when the bistable device is expected to be in the set state after the next falling clock; second means connected to the second latching circuit providing thereto a second signal when the bistable device is expected to be in the reset state after the next falling clock, and means operating the first and second latching circuits to latch in response to the first and second signals respectively if produced between rising and falling clock.

Claim 4

In a flip-flop circuit which includes a bistable device responsive to set and reset inputs and operating in response to trigger signals, the combination comprising: first means connected to assume a first particular state in response to inputs applied to the flip-flop circuit and to the bistable device therein, at a particular instant prior to a trigger signal, the inputs determining the state of the bistable device after this trigger signal; second means included in the first means and connected to cause the first means to assume a second particular state if the inputs change subsequent to the particular instant prior to the trigger signal; and means connected to provide an indication of the presence or absence of the second particular state.

Claim 5

In a flip-flop circuit which includes a bistable device responsive to set and reset inputs and operating in response to trigger signals, the combination comprising: first means connected to assume a first particular state in response to inputs applied to the flip-flop circuit and to the bistable device therein, at a particular instant prior to a trigger signal, the inputs determining the state of the bistable device after this trigger signal; second means included in the first means and connected to cause the first means to assume a second particular state if the inputs change subsequent to the particular instant prior to the trigger signal; and means connected to provide an indication of the presence or absence of the second particular state.

Claim 6

In a flip-flop circuit as set forth in claim 3 and receiving alternating true and false clock pulses, the bistable device being triggered when the clock pulse turns from true to false, the first means assuming a state when the clock pulse turns from false to true, the second means causing the first means to assume the second state when the inputs change during a true clock pulse.

Claim 7

In a flip-flop circuit as set forth in claim 3, the first means comprising a pair of latches, only one of them being set in response to a signal preceding each trigger signal, the second state being the concurrent set state of both latches, the flip-flop circuit including a third latch connected to be set upon concurrence of the set state of both latches of the pair.

Claim 8

In a flip-flop circuit as set forth in claim 3, including means to receive alternating true and false clock pulses, the bistable device being triggered when the clock turns from true to false, the first means including a pair of latches connected to receive the clock, one or the other of the pair being set as the first state of the first means upon change of the clock from false to true when the bistable device is respectively expected to be in the set or reset state at the next clock change from true to false by operation of the inputs at the time the clock changes from false to true, the second means causing both latches to set as the second state of the first means when there is a change in inputs during the true clock tending to deviate the state of the bistable device from the expected one.

Claim 9

In a flip-flop circuit as set forth in claim 3, the flip-flop, the first, second and last means being on an integrated circuit chip.

Claim 10

In a flip-flop circuit which includes a bistable device responsive to set, reset and clock signals for changing state in dependence upon set and/or reset signals at the time of a falling clock, the combination comprising: first and second latching circuits; first means connected to provide a first control signal representing the establishing or maintaining of the set state in the bistable device on falling clock; second means connected to provide a second control signal representing the establishing or maintaining of the reset state in the bistable device on falling clock; means for connecting the first means to set the first latching circuit in response to the first control signal when present during a particular period preceding each falling clock; means for connecting the second means to set the second latching circuit in response to the second control signal when present during the particular period preceding each falling clock; and means connected to be responsive to concurrent set states of the latching circuits at each falling clock.

Claim 11

In a flip-flop circuit which includes a bistable device responsive to set, reset and clock signals for changing state in dependence upon set and/or reset signals at the time of a falling clock, the combination comprising: first and second latching circuits; first means connected to provide a first control signal representing the establishing or maintaining of the set state in the bistable device on falling clock; second means connected to provide a second control signal representing the establishing or maintaining of the reset state in the bistable device on falling clock; means for connecting the first means to set the first latching circuit in response to the first control signal when present during a particular period preceding each falling clock; means for connecting the second means to set the second latching circuit in response to the second control signal when present during the particular period preceding each falling clock; and means connected to be responsive to concurrent set states of the latching circuits at each falling clock.