Signal buffer circuit arrangement

Claim 1

A signal buffer circuit arrangement for providing an interface between an output terminal of an integrated circuit and an external circuit, said integrated circuit being provided internally with at least two current paths, one of said current paths including a first transistor of one conductivity type and the other current path including a second transistor of the opposite conductivity type, said first and second transistors having their emitter-collector paths connected in series between supply lines and their emitters connected to said output terminal so that each of said first and second transistors is rendered separately conductive at different bias voltage levels that inhibit the conductivity of the other of said first and second transistors, said arrangement further comprising an input transistor having its base connected to receive an input signal, and its emitter and collector connected one each to the base of a respective one of said first and second transistors to feed thereto noninverted and inverted versions of said input signal, a load resistor external of said intergrated circuit connected to said output terminal, and means external of said integrated circuit for connecting said load resistor selectively to one of at least two bias voltage sources providing said different bias voltage levels such that one of said first and second conductors is biased for conduction and the other is cut-off.