US3790823A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-speed transistor digital gating
Assignee: AT&T Inc
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Filing: 1972-03-03
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Granted: 1974-02-05
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Expires: 1992-03-03
Abstract
Abstract A transistor digital gating circuit includes an output stage containing two transistors of opposite conductivity type which are held out of saturation at all times and an input stage containing two multiple-emitter transistors of opposite conductivity type which are kept in saturation continuously. The gate affords a high degree of isolation when disabled and avoids switching speed limitations which would be encountered if transistors were switched into and out of saturation.
Inventors
- 👤 B Briley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 15:14
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/013; H03K19/02; H03K19/08; H03K19/082; H03K19/088
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
159 words
A high-speed digital gate which comprises a pair of output transistors of opposite conductivity type having their emitter electrodes connected together and to a common output terminal and their collector electrodes connected to opposite sides of a direct voltage source poled to provide both of said output transistors with reverse collector current, a pair of input transistors of opposite conductivity type each having an emitter electrode connected to a common input terminal, resistive connections from the respective base electrodes of said input transistors to opposite sides of a direct voltage source poled to provide both of said input transistors with forward emitter and collector current, and means connecting the collector electrode of each of said input transistors to the base electrode of the one of Said output transistors of the same conductivity type, whereby digital signals pass from said common input terminal to said common output terminal without switching any of said transistors either into or out of saturation.
Claim 2
Dependent Claim
159 words
A high-speed digital gate which comprises a pair of output transistors of opposite conductivity type having their emitter electrodes connected together and to a common output terminal and their collector electrodes connected to opposite sides of a direct voltage source poled to provide both of said output transistors with reverse collector current, a pair of input transistors of opposite conductivity type each having an emitter electrode connected to a common input terminal, resistive connections from the respective base electrodes of said input transistors to opposite sides of a direct voltage source poled to provide both of said input transistors with forward emitter and collector current, and means connecting the collector electrode of each of said input transistors to the base electrode of the one of Said output transistors of the same conductivity type, whereby digital signals pass from said common input terminal to said common output terminal without switching any of said transistors either into or out of saturation.
Claim 3
Dependent Claim
28 words
A high-speed digital gate in accordance with claim 1 in which said output transistors have their collector electrodes connected directly to opposite sides of a direct voltage source.
Claim 4
Dependent Claim
21 words
A high-speed digital gate in accordance with claim 2 in which said output transistors have their emitter electrodes connected directly together.
Claim 5
Dependent Claim
23 words
A high-speed digital gate in accordance with claim 3 in which each of said resistive connections comprises the emitter-collector path of a transistor.
Claim 6
Dependent Claim
209 words
A high-speed digital which comprises a pair of output transistors of opposite conductivity type having their emitter electrodes connected together and to a common output terminal and their collector electrodes connected to opposite sides of a direct voltage source poled to provide both of said output transistors with reverse collector current, a pair of multiple emitter input transistors of opposite conductivity type having one emitter electrode each connected to a common input terminal and an additional emitter electrode each connected to a respective gating terminal, resistive connections from the respective base electrodes of said input transistors to opposite sides of direct voltage source poled to provide both of said input transistors with forward emitter and collector current, and means connecting the collector electrode of each of said input transistors to the base electrode of the one of said output transistors of the same conductivity type, whereby digital signals are passed from said common input terminal to said common output terminal without switching any of said transistors either into or out of saturation and said gate is disabled by potentials at said gating terminals providing said additional emitter electrodes of said input transistors with forward emitter current and enabled by potentials at said gating terminals removing said forward emitter current.
Claim 7
Dependent Claim
209 words
A high-speed digital which comprises a pair of output transistors of opposite conductivity type having their emitter electrodes connected together and to a common output terminal and their collector electrodes connected to opposite sides of a direct voltage source poled to provide both of said output transistors with reverse collector current, a pair of multiple emitter input transistors of opposite conductivity type having one emitter electrode each connected to a common input terminal and an additional emitter electrode each connected to a respective gating terminal, resistive connections from the respective base electrodes of said input transistors to opposite sides of direct voltage source poled to provide both of said input transistors with forward emitter and collector current, and means connecting the collector electrode of each of said input transistors to the base electrode of the one of said output transistors of the same conductivity type, whereby digital signals are passed from said common input terminal to said common output terminal without switching any of said transistors either into or out of saturation and said gate is disabled by potentials at said gating terminals providing said additional emitter electrodes of said input transistors with forward emitter current and enabled by potentials at said gating terminals removing said forward emitter current.
Claim 8
Dependent Claim
28 words
A high-speed digital gate in accordance with claim 5 in which said output transistors have their collector electrodes connected directly to opposite sides of a direct voltage source.
Claim 9
Dependent Claim
21 words
A high-speed digital gate in accordance with claim 6 in which said output transistors have their emitter electrodes connected directly together.
Claim 10
Dependent Claim
23 words
A high-speed digital gate in accordance with claim 7 in which each of said resistive connections comprises the emitter-collector path of a transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-02-04 | 1977-08-06 | 1978-02-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-02-04 | 1981-08-06 | 1982-02-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-02-04 | 1985-08-06 | 1986-02-05 | $7700.00 | Window Closed / Lapsed |