US3694666A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistor logic circuits
Assignee: AT&T Inc
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Filing: 1971-05-14
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Granted: 1972-09-26
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Expires: 1991-05-14
Abstract
Abstract A general purpose transistor logic circuit comprising an AND and an OR stage serially connected in either sequence. Each stage comprises multiemitter input transistor and a single emitter output transistor, the transistors of each stage being of the opposite conductivity type. Each stage provides an emitter follower output to achieve a substantial increase in switching speed and the combined stages effectively cancel voltage shifts occurring across each.
Inventors
- 👤 Bruce Edwin Briley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 01:14
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/088
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
183 words
A general purpose logic circuit combination comprising a first logic gate comprising a first transistor of one conductivity type having a plurality of emitters, a collector, and a base, a first reference potential source connected to said base, and a second transistor of said one conductivity type having an emitter, a collector connected to said first reference potential source, and a base connected to said collector of said first transistor; a second logic gate comprising a third transistor of the other conductivity type having a plurality of emitters one of which being connected to said emitter of said second transistor, a collector, and a base, a second reference potential source connected to said base of said last-mentioned transistor, and a fourth transistor of said other conductivity type having an emitter, a collector connected to said second reference potential source, and a base connected to said collector of said third transistor; an output terminal connected to said emitter of said fourth transistor; and a load resistor for said second transistor connected between the base of said third transistor and said second reference potential source.
Claim 2
Dependent Claim
183 words
A general purpose logic circuit combination comprising a first logic gate comprising a first transistor of one conductivity type having a plurality of emitters, a collector, and a base, a first reference potential source connected to said base, and a second transistor of said one conductivity type having an emitter, a collector connected to said first reference potential source, and a base connected to said collector of said first transistor; a second logic gate comprising a third transistor of the other conductivity type having a plurality of emitters one of which being connected to said emitter of said second transistor, a collector, and a base, a second reference potential source connected to said base of said last-mentioned transistor, and a fourth transistor of said other conductivity type having an emitter, a collector connected to said second reference potential source, and a base connected to said collector of said third transistor; an output terminal connected to said emitter of said fourth transistor; and a load resistor for said second transistor connected between the base of said third transistor and said second reference potential source.
Claim 3
Dependent Claim
24 words
A general purpose logic circuit combination as claimed in claim 1 in which said first and second transistors are of the NPN conductivity type.
Claim 4
Dependent Claim
24 words
A general purpose logic circuit combination as claimed in claim 1 in which said first and second transistors are of the PNP conductivity type.
References Cited (Backward Citations)
US3233125A
Cited
US3416003A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-09-26 | 1976-03-27 | 1976-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-09-26 | 1980-03-27 | 1980-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-09-26 | 1984-03-27 | 1984-09-26 | $7700.00 | Window Closed / Lapsed |