Method and apparatus for detecting errors in a data set

Claim 3

The method of claim 1 further comprising the steps of: correcting errors detected in the code set by: for each of the first and second code subsets: sequentially storing each of the data digits of said code subset upon the separation thereof from the code subset, and sequentially providing each of the stored data digits of said code subset after the code subset cyclic redundancy code for said code subset has been generated; generating a correction cyclic redundancy code of said selected form for the respective code subset cyclic redundancy code in synchronization with the provision of each of the data digits of said code subset; providing a correct signal when the correction cyclic redundancy code has a predetermined value indicative of an identified error in said code subset; correcting, in response to said correct signal, the stored data digit being provided at the time the correct signal is being provided; and merging the data digits and corrected data digits of each of the first and second code subsets to form the data set, with each of the sequential data digits of the first code subset being sequentially interposed between the sequential data digits of the second code subset.

Claim 4

The method of claim 2 wherein the step of encoding the data set to form the code set further comprises the steps of: generating, for each of the first and second code subsets, a parity digit indicative of the parity of said code subset; and appending said parity digits to the ends of the respective code subsets to provide said code subset with a predetermined parity; wherein the step of decoding the code set to detect errors further comprises the steps of: generating, for each of the first and second code subsets, a parity digit indicative of the parity of said code subset; and wherein the step of correcting errors detected in the code set further comprises the step of: disabling the production of the correct signal when the parity digit generated for the respective code subset indicates a parity different from said predetermined parity.

Claim 5

The method of claim 1, 2 or 3 wherein the selected form for generating the cyclic redundancy codes, for data subsets of length less than 256 digits, comprises a generator polynomial G(X) of the form: G(X)=(X.sup.8 +X.sup.4 +X.sup.3 +X.sup.2 +1).

Claim 8

The method of claim 5 further comprising the steps of: sequentially storing each of the data digits of said code subsets upon the separation thereof from the code set, and sequentially providing each of the stored data digits of said code subsets after the code subset cyclic redundancy codes for said code subsets have been generated; generating a correction cyclic redundancy code of said selected form for each of the respective code subset cyclic redundancy codes in synchronization with the provision of each of the data ditis of said code subset; providing a correct signal when either of the correction cyclic redundancy codes has a predetermined value indicative of an identified error in said code subset; correcting, in response to said correct signal, the stored data digit being provided at the time the correct signal is provided, by inverting said data digit; and merging the data digits and corrected data digits of each of the first and second code subsets to form the data set, with each of the sequential data digits of the first code subset being sequentially interposed between the sequential data digits of the second code subset.

Claim 9

The method of claim 6 further defined to include the steps of: generating, for each of the first and second code subsets upon the formation thereof, a parity digit indicative of the parity of said code subset; appending said parity digits to the ends of the respective code subsets to provide said code subsets with a predetermined parity; generating, for each of the first and second code subsets upon the separation thereof from the code set, a parity digit indicative of the parity of said code subset; and disabling the production of the correct signal when the parity digit generated for the respective code subset indicates a parity different from said predetermined parity.

Claim 10

The method of claim 5, 6 or 7 wherein the selected form for generating the cyclic redundancy codes, for data subsets of length less than 256 digits, comprises a generator polynomial G(X) of the form; G(X)=(X.sup.8 +X.sup.4 +X.sup.3 +X.sup.2 +1).

Claim 11

Apparatus for detecting errors in a data set of sequential binary digits, comprising: data set demultiplexing means for separating alternating ones of the sequential binary digits into first and second data subsets; data subset CRC generating means for generating a binary cyclic redundancy code of a selected form for each of said data subsets; gating means for appending each cyclic redundancy code to the end of the respective data subset to form a corresponding code subset; multiplexing means for merging the first and second code subsets to form a code set by sequentially interposing the digits of the first code subset between the digits of the second code subset, said multiplexing means providing the code set for operation thereon in a manner having a significant probability of altering at least one of the digits of the code set; code set demultiplexing means for separating alternating ones of the digits of the code set into the first and second code subsets; code subset CRC generating means for generating a binary cyclic redundancy code of said selected form for each of said code subsets; and error gating means for providing an error signal in response to a code subset cyclic redundancy code having a value indicative of an error in said code subset.

Claim 12

Apparatus for detecting errors in a data set of sequential binary digits, comprising: data set demultiplexing means for separating alternating ones of the sequential binary digits into first and second data subsets; data subset CRC generating means for generating a binary cyclic redundancy code of a selected form for each of said data subsets; gating means for appending each cyclic redundancy code to the end of the respective data subset to form a corresponding code subset; multiplexing means for merging the first and second code subsets to form a code set by sequentially interposing the digits of the first code subset between the digits of the second code subset, said multiplexing means providing the code set for operation thereon in a manner having a significant probability of altering at least one of the digits of the code set; code set demultiplexing means for separating alternating ones of the digits of the code set into the first and second code subsets; code subset CRC generating means for generating a binary cyclic redundancy code of said selected form for each of said code subsets; and error gating means for providing an error signal in response to a code subset cyclic redundancy code having a value indicative of an error in said code subset.

Claim 13

The apparatus of claim 9 further comprising: register means for sequentially storing the data digits of the first and second code subsets provided by the code set demultiplexing means, and for sequentially providing the stored data digits after the code subset CRC generating means have completed the generation of the code subset cyclic redundancy codes, the code subset CRC generating means generating a correction cyclic redundancy code of said selected form for each of the respective code subset cyclic redundancy codes in synchronization with the provision by the register means of each of the data digits of said code subset; correct gating means for providing a correct signal when either of the correction cyclic redundancy codes has a predetermined value indicative of an identified error in said code subset; means for correcting, in response to said correct signal, the data digit being provided by the register means at the time the correct signal is provided by the correct gating means, by inverting said data digit; and multiplexing means for merging the data digits and corrected data digits of each of the first and second code subsets to form the data set, with each of the sequential data digits of the first code subset being sequentially interposed between the sequential data digits of the second code subset.

Claim 14

The apparatus of claim 10 further comprising: data set parity generating means for generating a parity digit indicative of the parity of each of the first and second data subsets, the gating means appending said parity digits to the ends of the respective data subsets to provide each a predetermined parity; and code subset parity generating means for generating a parity digit indicative of the parity of each of the first and second code subsets provided by the code set demultiplexing means, the correct gating means being unable to produce said correct signal when the parity digit generated by the code subset parity generating means indicates a parity for the respective code subset different from said predetermined parity.

Claim 15

The apparatus of claim 9, 10 or 11 wherein each of the CRC generating means generates, for data subsets of length less than 256 digits, the respective cyclic redundancy codes via a generator polynomial G(X) of the form: G(X)=(X.sup.8 +X.sup.4 +X.sup.3 +X.sup.2 +1).