Receiver for simultaneously transmitted clock and auxiliary signals

Claim 1

An improved receiver for clock signals (HC) of frequency F, and auxiliary signals (HS) of frequency f, f being a submultiple of F and related thereto by the relationship F=kf, where k is an integer, k=2, 3, 4, . . . , said signals being transmitted together by means of a modified clock signals (HM) in which one pulse is omitted every k clock signal pulses, said modified clock signals being transmitted simultaneously over three, nominally identical, transmission lines (e.g. as signals HM1, HM2, and HM3), said receiver being of a type that comprises: (a) a selection circuit (1), including a majority logic circuit, connected to said three transmission lines for generating a normal, modified clock signal (H) even if one of the received, modified clock signals (HM1, HM2, or HM3) is abnormal; and (b) a signal separation circuit (2), connected to the output of said selection circuit, for reconstituting said clock signals (HC) and said auxiliary signals (HS), (c) an alarm circuit having three inputs, each connected to a corresponding one of said three transmission lines, at the input to said selection circuit, for generating an encoded digital alarm signal upon failure of any one of said three transmission lines, said alarm circuit including means for detecting signal non-conformities which comprises: (1) three detector circuits (14,15,16), each connected to a corresponding one of said three transmission lines, for detecting the absence of incoming signal pulses; (2) first (18) and second (19) comparison circuits, respectively connected to the first (HM1) and second (HM2) ones of said three transmission lines, for comparing the signals transmitted over said first and second transmission lines with the signal transmitted over said third transmission line (HM3), delayed by a quarter period in a delay line (17), said delayed signal acting as a reference signal for each of the two other transmitted signals; and (3) a logic circuit (20,21) having inputs connected to the outputs of said first and second comparison circuits (18,19) to the output of the detector circuit (16) associated with said delay circuit (17), for generating said encoded alarm signals.