Josephson Atto-Weber switch

Claim 2

A Josephson junction circuit comprising a Josephson junction gate capable of being switched between a low impedance state at V=0 and a high impedance state at V≠0, bias electrode means (14) for applying primary bias current to said gate, an output line (12) having an impedance connected to said gate, control electrode means (10) for applying control current to said gate for switching said gate from V=0 to V≠0 and to divert said primary bias current to said output line, characterized in that said gate comprises at least three circuit branches interconnected at three nodes (N1, N2, N3), said first node being connected to said control electrode means and said second node being connected to said output line and to said bias electrode means, a first Josephson junction (J1) in the branch between said second and third nodes, a second Josephson junction (J2) in the branch between said first and second nodes, and a resistor (r) in the branch between said first and third nodes, the critical currents of said junctions and said primary bias current (I b ) being mutually adapted to initially bias said junctions into their V=0 states and to sequentially switch said junctions to V≠0, when said control current (I c ) is applied, thereby causing said primary bias current to flow into said output line and said control current to flow through said resistor and said third node.

Claim 3

The circuit of claim 1 further characterized by auxiliary bias electrode means (16) for applying auxiliary bias current (I o ) to said first node in a direction opposite to that of said primary bias current, said auxiliary bias current also being mutually adapted along with said primary bias current and said critical currents to cause said junctions to switch sequentially to V≠0, after which said auxiliary bias current and said control current flow through said resistor and said third node.

Claim 4

The circuit of claims 1 or 2 wherein said output line has an inductance L, said gate has an inductance L' excluding the inductances of said junctions, and L>L'.

Claim 5

The circuit of claims 1 or 2 wherein said output line has a resistance R> r.

Claim 6

The circuit of claim 2 wherein said primary bias current and said control current are applied to said gate in the same direction, said control current has a low level I co and a relatively higher level I co +ΔI c , and said first and second junctions have critical currents I J1 and I J2 , respectively, which satisfy the following inequalities: (I.sub.b -I.sub.o +I.sub.co)<I.sub.J1 <(I.sub.b -I.sub.o)+I.sub.co +ΔI.sub.c I.sub.o -I.sub.co <I.sub.J2 <I.sub.b so that the current in said output line flows in the same direction as said control current.

Claim 7

The circuit of claim 2 wherein said primary bias current and said control current are applied to said gate in opposite directions, said control current has a low level I co and a relatively higher level (I co +ΔI c ), and said first and second junctions have critical currents I J1 and I J2 , respectively, which satisfy the following inequalities: (I.sub.b -I.sub.o -I.sub.co)<I.sub.J1 <I.sub.b I.sub.co +I.sub.o <I.sub.J2 <I.sub.co +ΔI.sub.c +I.sub.o so that the current in said output line flows in a direction opposite to that of said control current.

Claim 8

An INVERT circuit (FIG. 2) comprising a second circuit (G2) according to claim 2 wherein said primary bias current and said control current are applied to said gate in the same direction, said control current has a low level I co and a relatively higher level I co +ΔI c , and said first and second junctions have critical currents I J1 and I J2 , respectively, which satisfy the following inequalities: (I.sub.b -I.sub.o +I.sub.co)<I.sub.J1 <(I.sub.b -I.sub.o)+I.sub.co +ΔI.sub.c I.sub.o -I.sub.co <I.sub.J2 <I.sub.b so that the current in said output line of said second circuit flows in the same direction as said control current, a first circuit (G1) according to claim 2 wherein said primary bias current and said control current are applied to said gate in opposite directions, said control current has a low level I co and a relatively higher level (I co +ΔI c ), and said first and second juntions have critical currents I J1 and I J2 , respectively, which satisfy the following inequalities: (I.sub.b -I.sub.o -I.sub.co)<I.sub.J1 <I.sub.b I.sub.co +I.sub.o <I.sub.J2 <I.sub.co +ΔI.sub.c +I.sub.o so that the current in said output line of said first circuit flows in a direction opposite to that of said control current, said output line of said first circuit (G1) being connected to said control electrode means of said second circuit (G2).

Claim 9

An AND circuit (FIG. 3) comprising a pair of circuits according to claim 4 wherein the output line of one of said circuits is connected to the primary bias electrode means of the other of said circuits so as to supply said primary bias current to said other circuit.

Claim 10

An INVERT circuit (FIG. 4) comprising a pair of circuits according to claim 4 wherein said third node of one of said circuits is connected to said control electrode means of said other circuit.

Claim 11

A circuit (FIG. 7) according to claims 1 or 2 further including a third Josephson junction (J3), a resistor (r') connected in series with said third junction at a node (x), the series combination of said third junction and said second resistor being connected in parallel with one of said first or second junctions, and electrode means for applying control current (I' c ) to said node (x).

Claim 12

The circuit of claim 10 including electrode means for also applying another auxiliary bias current (I' o ) to said node (x).

Claim 13

A superconductive HUFFLE circuit (FIGS. 8, 9) comprising first and second Josephson junction gates (G1, G2) each having V=0 and V≠0 states, a critical current which when exceeded causes the gate to switch from V=0 to V≠0, and a drop-back level below which the gate switches from V≠0 to V=0, electrode means (n 1 , n 2 ) for applying DC bias current (I b ) to said gates, control electrode means (I c ) for selectively switching said gates between their V=0 and V≠0 states, and a passive network (R 1 , R 2 , L 3 ) coupling said gates to one another and responsive to the switching of states of at least one of said gates to V≠0 for applying a transient voltage or current to the other of said gates effective to reduce its voltage or current below the drop-back level thereof, characterized in that each of said gates comprises a superconductive circuit according to claims 1, 2, 5, or 6.

Claim 14

The circuit of claim 12 wherein said DC bias electrode means includes a first node (n 1 ) for applying bias current to said gates and a second node (n 2 ) for extracting bias current from said gates, said passive network comprises a first resistor (R 1 ) connected between said first node (n 1 ) and a common third node (n 3 ) a second resistor (R 2 ) connected between said second node (n 2 ) and said common node (n 3 ), and inductance means (L 3 ) connected between a fourth node (n 4 ) and said common node (n 3 ), further characterized in that said second node (N 2 ) of one of said gates (G1) is connected to said first node (n 1 ) of said HUFFLE circuit, said third nodes (N 3 ) of both of said gates are connected to said fourth node (n 4 ) of said HUFFLE circuit, and said second node (N 2 ) of said other gate (G2) is connected to said second node (n 2 ) of said HUFFLE circuit, so that said output lines of said gates supply current through said resistors (R 1 , R 2 ) to said inductance means (L 3 ).

Claim 15

The circuit (FIG. 9) of claim 13 further including a low impedance circuit path connecting said control electrode means of said gates to one another.

Claim 16

A memory circuit (FIG. 10) comprising a circuit according to claim 1, a totally superconductive path connected in parallel with said first junction and including said fanout line for carrying a persistent current, and means for sensing the presence or absence of said persistent current.

Claim 17

A Josephson junction circuit comprising a Josephson junction gate capable of being switched between a low impedance state at V=0 and a high impedance state at V≠0, bias electrode means (14) for applying primary bias current to said gate, an output line (12) connected to said gate, said output line having an impedance, control electrode means (10) for applying control current to said gate for switching said gate from V=0 to V≠0 and to divert said primary bias current to said output line, characterized in that said gate comprises at least three circuit branches interconnected at three nodes (N1, N2, N3) forming a loop circuit, said first node being connected to said control electrode means and said second node being connected to said output line, and said bias electrode means being adapted to inject said primary bias current into said loop circuit, a first Josephson junction (J1) in the branch between said second and third nodes, a second Josephson junction (J2) in the branch between said first and second nodes, and a resistor (r) in the branch between said first and third nodes, the critical currents of said junctions and said primary bias current (I b ) being mutually adapted to initially bias said junctions into their V=0 states and to sequentially switch said junctions to V≠0, when said control current (I c ) is applied, thereby causing said primary bias current to flow into said output line and said control current to flow through said resistor and said third node.

Claim 18

A Josephson junction circuit comprising a Josephson junction gate capable of being switched between a low impedance state at V=0 and a high impedance state at V≠0, bias electrode means (14) for applying primary bias current to said gate, an output line (12) connected to said gate, said output line having an impedance, control electrode means (10) for applying control current to said gate for switching said gate from V=0 to V≠0 and to divert said primary bias current to said output line, characterized in that said gate comprises at least three circuit branches interconnected at three nodes (N1, N2, N3) forming a loop circuit, said first node being connected to said control electrode means and said second node being connected to said output line, and said bias electrode means being adapted to inject said primary bias current into said loop circuit, a first Josephson junction (J1) in the branch between said second and third nodes, a second Josephson junction (J2) in the branch between said first and second nodes, and a resistor (r) in the branch between said first and third nodes, the critical currents of said junctions and said primary bias current (I b ) being mutually adapted to initially bias said junctions into their V=0 states and to sequentially switch said junctions to V≠0, when said control current (I c ) is applied, thereby causing said primary bias current to flow into said output line and said control current to flow through said resistor and said third node.

Claim 19

The circuit of claim 16 further characterized in that said bias electrode means is adapted to inject said primary bias current into the circuit branch which is connected between said first and second nodes.