Scan converter utilizing discrete differentially coded signals

Claim 2

A scan rate converter, comprising: (A) input section means operable in both a fast scan conversion and a slow scan conversion mode, said input section means for: (1) sampling an input FSTV signal at a fast scan rate when said input section means is operated in said fast scan conversion mode, said input FSTV signal including a plurality of lines of video information; (2) sampling an input SSTV signal at a slow scan rate when said input section means is operated in said slow scan conversion mode, said input SSTV signal including a plurality of lines of video information; and (3) generating a discrete differential coded signal responsive to each said sampling of said input FSTV and input SSTV signals when said input section means is operated in said fast scan and slow scan modes of operation, respectively, such that each line of video information being sampled is divided into a plurality of discrete differential coded signals, each of said discrete differential coded signals having a magnitude determined by the difference between the actual magnitude of the FSTV or SSTV signal being sampled at the sampling instant corresponding to the discrete differential coded signal in question and a predicted magnitude of the FSTV or SSTV signal being sampled at the sampling instant corresponding to the discrete differential coded signal in question, the value of said predicted magnitude of the FSTV or SSTV signal being sampled being reset to a predetermined value at each sampling instant corresponding to the first discrete differential coded signal in a line of video information being sampled, (B) memory section means operable in a read and a write mode of operation, said memory section means for: (1) storing each of said discrete differential coded signals generated by said input section means when said memory section means is operated in said write mode; and (2) reading said discrete differential coded signals stored in said memory section means out of said memory section means when said memory section means is operated in said read mode, said discrete differential coded signals stored in said memory section means being read out of said memory section means at both said fast scan and said slow scan sampling rates in a time multiplexed manner; and (C) output section means for: (1) converting said discrete differential coded signals read out of said memory section means at said fast scan rate into an output FSTV signal; and (2) converting said discrete differential coded signals read out of said memory section means at said slow scan rate into an output SSTV signal.

Claim 3

The scan rate converter of claim 1 wherein said input section means comprises: (A) a discrete differential coding circuit operable in a fast scan and a slow scan conversion mode, said discrete differential coding circuit: (1) sampling the magnitude of said input FSTV signal at each of a plurality of fast scan sampling instants when said discrete differential coding circuit is operated in said fast scan conversion mode, the frequency of said fast scan sampling instants being equal to said fast scan sampling rate; and (2) sampling the magnitude of said input SSTV signal at each of a plurality of slow scan sampling instants when said discrete differential coding circuit is operated in said slow scan conversion mode, the frequency of said slow scan sampling instants being equal to said slow scan sampling rate; and (B) control means for selectively operating said discrete differential coding circuit in said fast scan or said slow scan conversion modes.

Claim 4

The scan rate converter of claim 2 wherein said discrete differential coding circuit comprises: (A) feedback section means for: (1) generating a predicted FSTV signal representative of the predicted magnitude of said input FSTV signal at each successive fast scan sampling instant when said discrete differential coding circuit is operated in said fast scan conversion mode, said predicted FSTV signal corresponding to said predicted magnitude when said converter is operated in said fast scan conversion mode; and (2) generating a predicted SSTV signal representative of the predicted magnitude of said input SSTV signal at each successive slow scan sampling instant when said discrete differential coding circuit is operated in said slow scan conversion mode, said predicted SSTV signal corresponding to said predicted magnitude when said converter is operated in said slow scan conversion mode; and (B) encoding section means for: (1) generating a succession of discrete differential coded signals, each of said discrete differential coded signals being representative of the difference between the magnitude of said predicted FSTV signal and said input FSTV signal at respective ones of said fast scan sampling instants when said discrete differential coding circuit is operated in said fast scan conversion mode; and (2) generating a sequence of discrete differential coded signals, each of said discrete differential coded signals being representative of the difference between the magnitude of said predicted SSTV signal and said input SSTV signal at a respective one of said slow scan sampling instants when said discrete differential coding circuit is operated in said slow scan conversion mode.

Claim 5

The scan rate converter of claim 3, wherein said feedback section means generates each said predicted FSTV and SSTV signal as a function of the last generated discrete differential coded signal when said discrete differential coding circuit is operated in said fast scan and slow scan conversion modes, respectively.

Claim 6

The scan rate converter of claims 3 or 4, wherein said encoding section means comprises: (A) difference amplifier means for generating an analog difference signal representative of the instantaneous difference in the magnitude of said input SSTV and FSTV signals and the magnitude of said predicted FSTV and SSTV signals when said discrete differential coding circuit is operated in said fast scan and slow conversion modes, respectively; and (B) digital quantizer means responsive to said analog difference signal for classifying the magnitude of said difference signal into one of a plurality of error categories and for generating a digital output signal representative of said classification, said digital output signal defining said discrete differential coded signal.

Claim 7

The scan rate converter of claim 5, wherein said encoding section means further comprises a latch circuit for latching said output signal generated said quantizer means at each of said fast scan sampling instants when said discrete differential coding circuit is operated in said fast scan conversion mode and for latching said output signal generated by said quantizer means at each of said slow scan sampling instants when said discrete differential coding circuit is operated in said slow scan conversion mode.

Claim 8

The scan rate converter of claim 6, wherein said encoding section means further comprises an encoder for encoding the output of said latch circuit in such a manner as to reduce the number of bits in said discrete differential coded signal.

Claim 9

The scan rate converter of claim 4, wherein said feedback section comprises: (A) decoder/weigher means responsive to said discrete differential coded signals for generating an output signal representative of the predicted change in magnitude between the last generated predicted FSTV and SSTV signals and the next generated predicted FSTV and SSTV signals when said discrete differential encoding circuit is operated in said fast scan and slow scan conversion modes, respectively; (B) storage register means for storing the magnitude of the last generated predicted FSTV and SSTV signals when said discrete differential coding circuit is operated in said fast scan and slow scan modes, respectively; and (C) adder means for adding said signal stored in said storage register means and said signal generated by said decoder/weigher means and for generating an output signal representative of the predicted FSTV and SSTV signals at the next fast scan and slow scan sampling instants when said discrete differential coding circuit is operated in said fast scan and slow scan conversion modes, respectively.

Claim 10

The scan rate converter of claim 8, wherein said decoder/weigher means, said storage register means, and said adder means are digital circuit elements and said output signal generated by said adder means is applied to a digital to analog converter means which generates said analog predicted FSTV and SSTV signals when said discrete differential coding circuit is operated in said fast scan and slow scan conversion modes, respectively.

Claim 11

The scan rate converter of claim 1 wherein said memory section means comprises: digital memory means for storing discrete differential coded signals applied to its data input in storage locations identified by pixel and line addresses applied to its pixel and line address inputs whenever write pulses are applied to its read/write input; and address generating circuit means for generating fast pixel and line address signals and slow pixel line address signals in a time multiplexed manner, said fast and slow pixel and line address signals being applied to said pixel and line address inputs of said digital memory means; and read/write timing circuit means for applying fast scan write pulses to said read/write input of said digital memory means when said fast pixel and line address signals are applied to said pixel and line address inputs of said digital memory means and for applying slow scan write pulses to said rewrite input of said digital memory means when said fast pixel and line addresses are applied to said pixel and line addresses of said digital memory means; said digital memory means reading said discrete differential coded signals stored in said digital memory means being read out of said memory means when neither said fast scan or said slow scan write pulses are applied to said read/write input of said memory means, said discrete differential coded signals stored in said digital memory means being read out of said memory means at both said fast scan and said slow scan sampling rates in a time multiplex manner.

Claim 12

The scan rate converter of claim 10 wherein said memory section means further includes multiplexer means for applying said discrete differential coded signals to said output section means when said discrete differential coded signals are read out of said digital memory means and for applying said discrete differential signals generated by said input section means to said output section means when said discrete differential coded signals are being read into said digital memory means.

Claim 13

The scan rate converter of claim 1 wherein said output section means comprises: fast scan output circuit means for converting the discrete differential coded signals read out of said memory section means at said fast scan sampling rate into an FSTV video output signal; and slow scan output means responsive to said discrete differential coded signals read out of said memory section means at said fast scan sampling rate for generating an FM SSTV output signal.

Claim 14

The scan rate converter of claims 3 or 4, wherein said feedback section means includes means for resetting said predicted FSTV and SSTV signals to a predetermined value at the beginning of each line of video information being sampled when said converter is operated in said FSTV and SSTV scan conversion modes, respectively.

Claim 15

A scan rate converter, comprising: (A) input section means operable in both a fast scan conversion and a slow scan conversion mode, said input section means for: (1) sampling an input FSTV signal at a fast scan rate when said input section means is operated in said fast scan conversion mode; (2) sampling an input SSTV signal at a slow scan rate when said input section means is operated in said slow scan conversion mode; and (3) generating a discrete differential coded signal responsive to each said sampling of said input FSTV and input SSTV signals when said input section means is operated in said fast scan and slow scan modes of operation, respectively; (B) memory section means operable in a read and a write mode of operation, said memory section means for: (1) storing each of said discrete differential coded signals generated by said input section means when said memory section means is operated in said write mode; and (2) reading said discrete differential coded signals stored in said memory section means out of said memory section means when said memory section means is operated in said read mode, said discrete differential coded signals stored in said memory section means being read out of said memory section means at both said fast scan and said slow scan sampling rates in a time multiplexed manner; and (C) output section means for: (1) converting said discrete differential coded signals read out of said memory section means at said fast scan rate into an output FSTV signal; and (2) converting said discrete differential coded signals read out of said memory section means at said slow scan rate into an output SSTV signal; (D) said input section means comprising: (1) a discrete differential coding circuit operable in a fast scan and a slow scan conversion mode, said discrete differential coding circuit: (a) sampling the magnitude of said input FSTV signal at each of a plurality of fast scan sampling instants when said discrete differential coding circuit is operated in said fast scan conversion mode, the frequency of said fast scan sampling instant being equal to said fast scan sampling rate; and (b) sampling the magnitude of said input SSTV signal at each of a plurality of slow scan sampling instants when said discrete differential coding circuit is operated in said flow scan conversion mode, the frequency of said slow scan sampling instants being equal to said slow scan sampling rate; and (2) control means for selectively operating said discrete differential coding circuit and said fast scan or said slow scan conversion modes as selected; (E) said discrete differential coding circuit comprising: (1) feedback section means for: (a) generating a predicted FSTV signal representative of the predicted magnitude of said input FSTV signal at each successive fast scan sampling instant when said discrete differential coding circuit is operated in said fast scan conversion mode; and (b) generating a predicted SSTV signal representative of the predicted magnitude of said input SSTV signal at each successive slow scan sampling instant when said discrete differential coding circuit is operated in said slow scan conversion mode; and (2) encoding section means for: (a) generating a succession of discrete differential coded signals, each of said discrete differential coded signals being representative of the difference between the magnitude of said predicted FSTV signal and said input FSTV signal at respective ones of said fast scan sampling instants when said discrete differential coding circuit is operated in said fast scan conversion mode; and (b) generating a sequence of discrete differential coded signals, each of said discrete differential coded signals being representative of the difference between the magnitude of said predicted SSTV signal and said input SSTV signal at a respective one of said flow scan sampling instants when said discrete differential coding circuit is operated in said flow scan mode; (F) said feedback section means generating each said predicted FSTV and SSTV signal as a function of the last generated discrete differential coding circuit when operated at said fast scan and slow scan conversion modes, respectively; and (G) said feedback section means comprising: (1) decoder/weigher means responsive to said discrete differential coded signals for generating an output signal representative of the predicted change in magnitude between the last generated predicted FSTV and SSTV signals and the next generated predicted FSTV and SSTV signals when said discrete differential coding circuit is operated in said fast scan and slow scan conversion modes, respectively; (2) storage register means for storing the magnitude of the last generated predicted FSTV and SSTV signals when said discrete differential coding circuit is operated in said fast scan and slow scan modes, respectively; and (3) adder means for adding said signal stored in said storage register means and said signal generated by said decoder/weigher means and for generating an output signal representative of the predicted FSTV and SSTV signals at the next fast scan and slow scan sampling instants when said discrete differential coding circuit is operated in said fast scan and slow scan conversion modes, respectively.

Claim 16

A scan rate converter, comprising: (A) input section means operable in both a fast scan conversion and a slow scan conversion mode, said input section means for: (1) sampling an input FSTV signal at a fast scan rate when said input section means is operated in said fast scan conversion mode; (2) sampling an input SSTV signal at a slow scan rate when said input section means is operated in said slow scan conversion mode; and (3) generating a discrete differential coded signal responsive to each said sampling of said input FSTV and input SSTV signals when said input section means is operated in said fast scan and slow scan modes of operation, respectively; (B) memory section means operable in a read and a write mode of operation, said memory section means for: (1) storing each of said discrete differential coded signals generated by said input section means when said memory section means is operated in said write mode; and (2) reading said discrete differential coded signals stored in said memory section means out of said memory section means when said memory section means is operated in said read mode, said discrete differential coded signals stored in said memory section means being read out of said memory section means at both said fast scan and said slow scan sampling rates in a time multiplexed manner; and (C) output section means for: (1) converting said discrete differential coded signals read out of said memory section means at said fast scan rate into an output FSTV signal; and (2) converting said discrete differential coded signals read out of said memory section means at said slow scan rate into an output SSTV signal; (D) said input section means comprising: (1) a discrete differential coding circuit operable in a fast scan and a slow scan conversion mode, said discrete differential coding circuit: (a) sampling the magnitude of said input FSTV signal at each of a plurality of fast scan sampling instants when said discrete differential coding circuit is operated in said fast scan conversion mode, the frequency of said fast scan sampling instant being equal to said fast scan sampling rate; and (b) sampling the magnitude of said input SSTV signal at each of a plurality of slow scan sampling instants when said discrete differential coding circuit is operated in said flow scan conversion mode, the frequency of said slow scan sampling instants being equal to said slow scan sampling rate; and (2) control means for selectively operating said discrete differential coding circuit and said fast scan or said slow scan conversion modes as selected; (E) said discrete differential coding circuit comprising: (1) feedback section means for: (a) generating a predicted FSTV signal representative of the predicted magnitude of said input FSTV signal at each successive fast scan sampling instant when said discrete differential coding circuit is operated in said fast scan conversion mode; and (b) generating a predicted SSTV signal representative of the predicted magnitude of said input SSTV signal at each successive slow scan sampling instant when said discrete differential coding circuit is operated in said slow scan conversion mode; and (2) encoding section means for: (a) generating a succession of discrete differential coded signals, each of said discrete differential coded signals being representative of the difference between the magnitude of said predicted FSTV signal and said input FSTV signal at respective ones of said fast scan sampling instants when said discrete differential coding circuit is operated in said fast scan conversion mode; and (b) generating a sequence of discrete differential coded signals, each of said discrete differential coded signals being representative of the difference between the magnitude of said predicted SSTV signal and said input SSTV signal at a respective one of said flow scan sampling instants when said discrete differential coding circuit is operated in said flow scan mode; (F) said feedback section means generating each said predicted FSTV and SSTV signal as a function of the last generated discrete differential coding circuit when operated at said fast scan and slow scan conversion modes, respectively; and (G) said feedback section means comprising: (1) decoder/weigher means responsive to said discrete differential coded signals for generating an output signal representative of the predicted change in magnitude between the last generated predicted FSTV and SSTV signals and the next generated predicted FSTV and SSTV signals when said discrete differential coding circuit is operated in said fast scan and slow scan conversion modes, respectively; (2) storage register means for storing the magnitude of the last generated predicted FSTV and SSTV signals when said discrete differential coding circuit is operated in said fast scan and slow scan modes, respectively; and (3) adder means for adding said signal stored in said storage register means and said signal generated by said decoder/weigher means and for generating an output signal representative of the predicted FSTV and SSTV signals at the next fast scan and slow scan sampling instants when said discrete differential coding circuit is operated in said fast scan and slow scan conversion modes, respectively.