US4051530A
Expired / Lapsed
US
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Frame-to-frame coding system
Assignee: NTT Inc
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Filing: 1975-10-20
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Granted: 1977-09-27
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Expires: 1995-10-20
Abstract
Abstract An input video signal is fed to a substracter wherein a difference is taken between the input and the output from a frame memory to provide a difference signal, the magnitude of which is controlled by a magnitude adjuster. The controlled output is then fed to a threshold circuit, from which a significant difference signal is derived which has a magnitude above a given level. The significant difference signal is quantized by an encoder into a code having a reduced number of bits as compared with the inputted significant difference signal. The quantized code is written into a buffer memory, and is read out therefrom at a uniform bit rate to a transmission line. A sum of a signal indicative of the representative level of the quantized code from the encoder and the output of the frame memory is formed in an adder, and the sum signal is written into the frame memory and read out subsequently or after one frame. The occupancy of the buffer memory is detected to provide a control over the magnitude adjuster in accordance with the detected value so as to prevent an overflow from the buffer memory. A signal to refresh the frame memory located on the receiving side is transmitted by writing the output of the adder into the buffer memory after switching from the output of the encoder to the output of the adder.
Inventors
- 👤 Hideo Kuroda
- 👤 Fumio Kanaya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:12
CPC Classifications
H; H04; H04N; H04N19/00; H04N19/10; H04N19/102; H04N19/124; H04N19/50; H04N19/503
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
266 words
An interframe coding system comprising: a subtracter for outputting a difference signal between an input signal and an output from a frame memory; a magnitude adjuster connected with the output of the subtracter for controlling the magnitude of the difference signal; an encoder connected with the output of the magnitude adjuster for quantizing the output therefrom to output a code having a smaller number of bits than that of the difference signal, and including means for converting the code into a representative level output signal having the same number of bits as that of the difference signal and indicative of a quantization level; an adder connected with the output of the encoder for adding together the representative level output signal and the output from the frame memory; the frame memory being connected with the output of the adder for delaying its output by one frame of the input signal; a combination of a synchronizing signal generator and an address generator for deriving from the input signal a synchronizing signal and an address signal for defining the position of the output code of the encoder on the frame; a buffer memory connected with the output of the encoder for receiving the code output therefrom and the outputs from the synchronizing signal generator and the address generator, which are written into the buffer memory and read out therefrom as code signals of a uniform bit rate; and a controller for monitoring the occupancy of the buffer memory to thereby control the magnitude adjuster in accordance with the occupancy so as to prevent an overflow of the buffer memory.
Claim 2
Dependent Claim
266 words
An interframe coding system comprising: a subtracter for outputting a difference signal between an input signal and an output from a frame memory; a magnitude adjuster connected with the output of the subtracter for controlling the magnitude of the difference signal; an encoder connected with the output of the magnitude adjuster for quantizing the output therefrom to output a code having a smaller number of bits than that of the difference signal, and including means for converting the code into a representative level output signal having the same number of bits as that of the difference signal and indicative of a quantization level; an adder connected with the output of the encoder for adding together the representative level output signal and the output from the frame memory; the frame memory being connected with the output of the adder for delaying its output by one frame of the input signal; a combination of a synchronizing signal generator and an address generator for deriving from the input signal a synchronizing signal and an address signal for defining the position of the output code of the encoder on the frame; a buffer memory connected with the output of the encoder for receiving the code output therefrom and the outputs from the synchronizing signal generator and the address generator, which are written into the buffer memory and read out therefrom as code signals of a uniform bit rate; and a controller for monitoring the occupancy of the buffer memory to thereby control the magnitude adjuster in accordance with the occupancy so as to prevent an overflow of the buffer memory.
Claim 3
Dependent Claim
99 words
The interframe coding system according to claim 1, further including a switching circuit connected between the encoder and the buffer memory for switching the input side of the buffer memory from the output of the encoder to the output of the adder, and means for periodically controlling the switching circuit to switch the input side of the buffer memory to the output of the adder every plurality of horizontal scanning lines of the input signal for a period of time of at least one of the horizontal scanning lines and sequentially shift the position of the horizontal scanning line.
Claim 4
Dependent Claim
63 words
The interframe coding system according to claim 1, further including a switching circuit connected between the encoder and the buffer memory, and means for producing an output when the occupancy of the buffer memory has become smaller than a predetermined value to switch the switching circuit from the output of the encoder to the output of the adder while the output is produced.
Claim 5
Dependent Claim
47 words
An interframe coding system according to claim 1, further including a variable word length code converter between the encoder and the buffer memory for performing a code conversion whereby, as the frequency of occurrence of a code increases, the number of bits in the code is smaller.
Claim 6
Dependent Claim
104 words
An interframe coding system according to claim 4, further including a switching circuit connected between the encoder and the variable word length code converter for switching the input of the variable word length code converter from the output of the encoder to the output of the adder, and means for periodically controlling the switching circuit to switch the input side of the buffer memory to the output of the adder every plurality of horizontal scanning lines of the input signal for a period of time of at least one of the horizontal scanning lines and sequentially shift the position of the horizontal scanning line.
Claim 7
Dependent Claim
35 words
An interframe coding system according to claim 1, further including a second magnitude adjuster connected between the encoder and the adder for controlling the magnitude in the opposite direction from the first mentioned magnitude adjuster.
Claim 8
Dependent Claim
34 words
An interframe coding system according to claim 6, further including a code generator which generates a code indicative of the controlled state of the second magnitude adjuster and supplies it to the buffer memory.
Claim 9
Dependent Claim
83 words
An interframe coding system according to claim 7, further including a circuit for detecting the code indicative of the controlled state of the second magnitude adjuster from the transmitted and received code, means for controlling the magnitude of the received code in the opposite direction from the control by the first mentioned magnitude adjuster and in accordance with the detected code, and means for adding the controlled code and the output from the frame memory together for decoding into a digital video signal.
Claim 10
Dependent Claim
44 words
An interframe coding system according to claim 1, further including a threshold circuit connected between the magnitude adjuster and the encoder for supplying a portion of the output from the adjuster which exceeds a given level to the encoder as a significant difference signal.
Claim 11
Dependent Claim
92 words
An interframe coding system according to claim 1 in which the magnitude adjuster comprises a plurality of suppression means for suppressing the difference signal by a given factor, the factor of one of the suppression means being different from that of any other suppression means, and means for selecting an output from these suppression means, and in which the controller comprises means for detecting the occupancy of the buffer memory over a plurality of occupancy levels, and means responsive to the detection means for producing a signal which controls the selection means.
References Cited (Backward Citations)
US3562744A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-09-26 | 1981-03-28 | 1981-09-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-09-26 | 1985-03-28 | 1985-09-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-09-26 | 1989-03-28 | 1989-09-27 | $7700.00 | Window Closed / Lapsed |