Patent US4270169A successfully refreshed from Google Patents.
US4270169A
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Array processor
Assignee: CAMBRIDGE PARALLEL PROCESSING Ltd
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Filing: 1979-03-15
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Granted: 1981-05-26
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Expires: 1999-03-15
Abstract
Abstract An array processor is described consisting of a plurality of modules connected together in rows and columns. Each module has at least one special terminal which, as well as providing a connection for transfer of data between adjacent modules, also provides an output which is combined with similar signals from the other modules in the same row, to form a row response signal. Alternate modules in each row are rotated by 180° with respect to each other, so that the special terminals on adjacent modules are connected in pairs. This reduces the complexity of the circuits for forming the row response signals.
Inventors
- 👤 David J. Hunt
- 👤 Stewart F. Reddaway
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 07:45
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F15/8023
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
203 words
An array processor comprising (a) a plurality of identical processing modules in rows and columns to form a two-dimensional rectangular array; (b) each module having a first set of terminals along a first edge of said module and a second set of terminals along a second edge of said module, said second edge being parallel to said first edge, said second set of terminals transferring signals which are functionally different from the signal transferred by said first set; (c) each module comprising means for producing response signals and means for coupling said response signals internally of the module to terminals of said first set of terminals; (d) the modules of alternate columns being rotated 180° with respect to each other so that the first sets of terminals of adjacent modules in the same row are opposite each other and also the second sets of terminals of adjacent modules in same row are opposite each other; (e) the mutually opposite terminals being connected together; (f) a plurality of gates; and (g) means for connecting each gate to a plurality of the interconnected mutually opposite pairs of terminals of the first sets of terminal whereby the outputs of the gates are the overall response signals.
Claim 2
Dependent Claim
203 words
An array processor comprising (a) a plurality of identical processing modules in rows and columns to form a two-dimensional rectangular array; (b) each module having a first set of terminals along a first edge of said module and a second set of terminals along a second edge of said module, said second edge being parallel to said first edge, said second set of terminals transferring signals which are functionally different from the signal transferred by said first set; (c) each module comprising means for producing response signals and means for coupling said response signals internally of the module to terminals of said first set of terminals; (d) the modules of alternate columns being rotated 180° with respect to each other so that the first sets of terminals of adjacent modules in the same row are opposite each other and also the second sets of terminals of adjacent modules in same row are opposite each other; (e) the mutually opposite terminals being connected together; (f) a plurality of gates; and (g) means for connecting each gate to a plurality of the interconnected mutually opposite pairs of terminals of the first sets of terminal whereby the outputs of the gates are the overall response signals.
Claim 3
Dependent Claim
80 words
An array processor according to claim 1 comprising means for receiving a routing code specifying a direction in which data is to be transferred between the first and second sets of terminals of adjacent modules in the array, means for transmitting said routing code to alternate columns of the array without modification, and means for modifying said routing code so as to reverse the direction specified thereby and for transmitting the modified code to the remaining columns of the array.
References Cited (Backward Citations)
US3287702A
Cited
US3287703A
Cited
US3312943A
Cited
US3296426A
Cited
US3308436A
Cited
US3364472A
Cited
US3473160A
Cited
US3537074A
Cited
US3544973A
Cited
US3582899A
Cited
US3936806A
Cited
US3815095A
Cited
US3979728A
Cited
US3970993A
Cited
US4065808A
Cited
US4174514A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-05-25 | 1984-11-24 | 1985-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-05-25 | 1988-11-24 | 1989-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-05-25 | 1992-11-24 | 1993-05-26 | $7700.00 | Window Closed / Lapsed |