US4268952A
Expired / Lapsed
US
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Method for fabricating self-aligned high resolution non planar devices employing low resolution registration
Assignee: International Business Machines Corp
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Filing: 1979-04-09
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Granted: 1981-05-26
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Expires: 1999-04-09
Abstract
Abstract A method is disclosed for fabricating structures having electrically conductive regions such as high resolution semiconductor device and circuit designs which require only low resolution alignment steps during fabrication. The method is used to fabricate metal semiconductor field effect transistors (MESFET) and metal oxide semiconductor field effect transistors (MOSFET) devices and incorporates the following features. A device with very small (i.e. submicron) dimensions is positioned in a relatively large device well such that the exact position of the device in its well is not critical. Isolation and interconnection of devices in different wells is achieved by standard masking and alignment techniques with a resolution corresponding to the larger dimensions of the device wells. All high resolution features of the device are contained in a single masking level, however, to separate and insulate different elements of the device at such small dimensions different height levels are used in the device so that one masking step can produce zero lateral spacing between the different device elements. The disclosure provides examples of the present method applied to the fabrication of a MESFET device and a MOSFET device and to the isolation and interconnection of single devices into large circuits on a semiconductor chip.
Inventors
- 👤 Fritz H. Gaensslen
- 👤 Eberhard A. Spiller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 07:25
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/87; H10P; H10P76/00; H10P76/20; H10P76/40
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
196 words
A method of fabricating structures containing high resolution conductive lines on a supporting substrate comprising the steps of: applying a layer of resist material over a horizontal substrate at a first height level, exposing patterns of selected regions of said resist material through a high resolution lithography mask, etching said patterned layer of resist material and said substrate down to at least one other different height level wherein selected regions of said patterned resist material and said substrate material subtending said selected regions of said resist material are not etched due to said patterned exposure and remain at a said first height level wherein said first and at least one other different height levels are separated by vertical walls formed by said etching step, and the step of applying a layer of conductive material to said horizontal surfaces of said structure at said first and at least one other different height levels to produce conductive patterns, which are electrically isolated from each other by said vertical walls formed by said etching step and wherein said electrically isolated conductive patterns are electrically isolated by substantially zero distance separation in the horizontal direction to provide said high resolution.
Claim 2
Independent Claim
196 words
A method of fabricating structures containing high resolution conductive lines on a supporting substrate comprising the steps of: applying a layer of resist material over a horizontal substrate at a first height level, exposing patterns of selected regions of said resist material through a high resolution lithography mask, etching said patterned layer of resist material and said substrate down to at least one other different height level wherein selected regions of said patterned resist material and said substrate material subtending said selected regions of said resist material are not etched due to said patterned exposure and remain at a said first height level wherein said first and at least one other different height levels are separated by vertical walls formed by said etching step, and the step of applying a layer of conductive material to said horizontal surfaces of said structure at said first and at least one other different height levels to produce conductive patterns, which are electrically isolated from each other by said vertical walls formed by said etching step and wherein said electrically isolated conductive patterns are electrically isolated by substantially zero distance separation in the horizontal direction to provide said high resolution.
Claim 3
Dependent Claim
63 words
A method for fabricating structures according to claim 1 wherein said structures are self-aligned high resolution semiconductor transistor devices and said method further includes the step of doping said surface of said substrate prior to applying said layer of resist material and exposing said layer of resist material through a high resolution lithography mask to define transistor device gate, source and drain elements.
Claim 4
Dependent Claim
103 words
A method for fabricating self-aligned high resolution semiconductor transistor devices according to claim 2 wherein said transistor device is a metal-semiconductor field-effect transistor and said method further includes the step of forming a device well area in the surface of said substrate by ion implantation of impurities through a low resolution mask prior to said doping step of claim 2, and wherein said step of applying a layer of electrically conductive material to said horizontal surfaces includes depositing conductive material through a low resolution mask to form contacts to said source and drain elements and to form the electrode of said gate element.
Claim 5
Dependent Claim
145 words
A method for fabricating self-aligned high resolution semiconductor transistor devices according to claim 2 wherein said transistor device is a metal-oxide-semiconductor field-effect transistor and said method further includes the step of applying a layer of silicon nitride over said surface of said substrate after said doping step to prevent oxidation of said source and drain elements, and wherein said layer of silicon nitride is etched along with said patterned layer of resist material and said substrate to form a pattern of silicon nitride over said doped substrate, the step of growing a gate oxide on the areas of said substrate exposed by said etching step, said gate oxide being grown only on said etched areas not covered by said pattern of silicon nitride, and the step of removing said silicon nitride prior to depositing said electrically conductive material for forming said electrically isolated conductive patterns.
Claim 6
Dependent Claim
114 words
A method for fabricating self-aligned high resolution semiconductor transistor devices according to claim 2 wherein a plurality of transistor devices each including a source drain and gate element are defined on said substrate using said high resolution lithography mask including the further steps of etching out said conductive material between each of said plurality of transistor devices, forming an oxide layer over said entire structure defining and etching contact holes over the source, drain and gate elements of each of said transistor devices using a coarse lithography mask depositing a layer of electrically conductive material over said structure and defining conductive material over said structure and defining conductive line patterns in said conductive layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1984-05-25 | 1984-11-24 | 1985-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-05-25 | 1988-11-24 | 1989-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-05-25 | 1992-11-24 | 1993-05-26 | $7700.00 | Window Closed / Lapsed |