Digital to analog conversion circuit including compensation FET'S

Claim 2

An integrated circuit for performing digital to analog conversions with improved accuracy, said circuit being comprised of: a plurality of resistors interconnected as an R-2R ladder network having N states with output legs for carrying currents I, I 2 1 , . . . I 2 N-1 respectively, where N is any integer; a pair of conductive output buses: and a total of N transistorized switch means coupled respectively to said N output legs of said ladder for switching said current received therefrom to a selectable one of said buses in response to externally generated digital signals; wherein the K switch means which couple the K most significant currents from said output legs to said buses have scaled resistances R, R×2 1 , . . . R×2 K-1 respectively where K is any integer less than N and R is any predetermined resistance; each of the remaining N-K switch means have unscaled resistances of R×2 K-1 ; and a compensating resistive means having a resistance of approximately two-thirds R×2 K-1 is included in the serial leg of stage K.

Claim 3

A circuit according to claim 1 wherein each of said switch means consists of a single pair of MOS transistors.

Claim 4

A circuit according to claim 1 wherein each of said compensating resistive means is a single MOS transistor.

Claim 5

A circuit according to claim 1 wherein the number N of said stages is at least 10.

Claim 6

A circuit according to claim 1 wherein said resistance R×2 K-1 is between 300-3,000 ohms.

Claim 7

An integrated circuit for performing digital to analog conversions with improved accuracy; said circuit being comprised of: a plurality of resistors interconnected as an R-2R ladder network having N stages with output legs for carrying currents I, I÷2 1 , . . . I÷2 N-1 respectively, where N is any integer; a pair of conductive output buses; and a total of N transistorized switch means coupled respectively to said N output legs of said ladder for switching said current received therefrom to a selectable one of said buses in response to externally generated digital signals; wherein the K switch means which couple the K most significant currents from said output legs to said buses have scaled resistances R, R×2 1 , . . . R×2 K-1 respectively where K is any integer less than N and R is any predetermined resistance; each of the remaining N-K switch means have unscaled resistances of R×2 K-1; a compensating resistive means having a resistance of approximately two-thirds R×2 K-1 is included in the serial leg of stage J of said ladder, where J is any integer between K and N; and a compensating resistive means having a resistance of approximately one-half R×2 K-1 is included in the serial leg of each of the stages K through J-1.

Claim 8

An integrated circuit for performing digital to analog conversions with improved accuracy; said circuit being comprised of: a plurality of resistors interconnected as an R-2R ladder network having N stages with output legs for carrying currents I, I÷2 1 , . . . I÷2 N-1 respectively, where N is any integer; a pair of conductive output buses; and a total of N transistorized switch means coupled respectively to said N output legs of said ladder for switching said current received therefrom to a selectable one of said buses in response to externally generated digital signals; wherein the K switch means which couple the K most significant currents from said output legs to said buses have scaled resistances R, R×2 1 , . . . R×2 K-1 respectively where K is any integer less than N and R is any predetermined resistance; each of the remaining N-K switch means have unscaled resistances of R×2 K-1; a compensating resistive means having a resistance of approximately two-thirds R×2 K-1 is included in the serial leg of stage J of said ladder, where J is any integer between K and N; and a compensating resistive means having a resistance of approximately one-half R×2 K-1 is included in the serial leg of each of the stages K through J-1.

Claim 9

A circuit according to claim 6 wherein each of said switch means consists of a single pair of MOS transistors.

Claim 10

A circuit according to claim 6 wherein each of said compensating resistive means is a single MOS transistor.

Claim 11

A circuit according to claim 6 wherein the number N of said stages is at least 10.

Claim 12

A circuit according to claim 6 wherein said resistance R×2 K-1 is between 300-3,000 ohms.