Low cost digital to synchro converter

Claim 2

In a digital to analog converter for converting digital input signals, each including a plurality of bits, to corresponding electrical analog output signals in accordance with first and second direct current reference voltages of equal amplitude and opposite signs and utilizing MOS FET switches, each MOS FET switch including input and output terminals for connection to the source-drain conducting path thereof and a gate terminal, and having a substantially common characteristic of a conducting resistance of said path which varies as a function of the voltage level being switched thereby and defining different first and second resistance values when switching the first and second reference voltages, respectively, and wherein said converter includes a plurality of said MOS FET switches corresponding to the plurality of bits of the digital input signals and selectively rendered conducting in response to digital input bit signals of a given digital input signal, applied to the gate terminals thereof, and an impedance network having a plurality of input terminals connected to the output terminals of corresponding ones of said plurality of MOS FET switches for receiving the outputs thereof when the latter are rendered conductive and respectively establishing analog voltages in the network in accordance with the digital bit positions thereof and the levels of the reference signals, said network summing the analog voltages established therein to produce an analog output signal for each digital input signal, the improvement comprising: first and second reference voltage supply terminals at which said first and second direct current reference voltages of equal amplitude and opposite sign, respectively, are provided, an inverter having an inverting input terminal and an output terminal, first and second further MOS FET switches respectively connecting, through the source-drain conducting paths thereof, corresponding ones of said first and second supply terminals to said inverting input terminal of said inverter, said further MOS FET switches having said substantially common conducting resistance characteristic as said plurality of MOS FET switches, means responsive to the digital input signal for identifying the required sign of the reference voltage, and selectively applying an enabling signal to the gate terminal of the corresponding one of said further MOS FET switches thereby to enable it to conduct the reference voltage of the required sign through the source-to-drain conducting path thereof for supply to said inverting input terminal of said inverter, said inverter producing the selected reference voltage in opposite sign at its output terminal; means connecting said output terminal of said inverter to the gate terminal of each of said plurality of MOS FET switches associated with said impedance network for supply of the selected reference voltage, inverted to the respectively opposite sign, to said plurality of MOS FET switches, whereby each said reference voltage is conducted in its original sign by the corresponding further MOS FET switch and in its inverted sign by the selected MOS FET switches associated with the impedance network, thereby establishing for said reference voltages of opposite signs a substantially common series resistance value of the sum of the first and second resistance values of said conducting MOS FET switches in the circuit from each reference voltage supply terminal to the impedance network.

Claim 3

A converter as recited in claim 1 wherein said inverter comprises an operational amplifier connected at the inverting input thereof to said selecting means.

Claim 4

A digital to analog converter for converting digital input signals, each including a plurality of bits, to corresponding electrical analog output signals in accordance with first and second direct current reference voltages to equal amplitude and opposite signs and utilizing MOS FET switches each including input and output terminals for connection to the source-drain conducting path thereof and a gate terminal, said switches having a substantially common characteristic of a conducting resistance of said path which varies as a function of the voltage level being switched thereby and defining first and second resistance values when switching the first and second reference voltages, respectively, and comprising: a plurality of said MOS FET switches corresponding to the plurality of bits, means for applying the digital input bit signals to the gate terminals of the corresponding MOS FET switches for selectively rendering said switches conductive, an impedance network having a plurality of input terminals connected to the output terminals of corresponding ones of said plurality of MOS FET switches for receiving the outputs thereof when the latter are rendered conductive and establishing an analog voltage therein in response to each MOS FET switch output received thereby, of a value corresponding to the digital bit position of the output and the levels of the reference signals, said network summing the analog voltages established therein in response to each digital input signal to produce a corresponding analog output signal, first and second reference voltage supply terminals at which said first and second direct current reference voltages of equal amplitude and opposite sign, respectively, are provided, means including an inverter having input and output terminals and receiving a selected one of said reference voltages at said input teRminal and producing the selected reference voltage in opposite sign at its output terminal for supply in common to the input terminals of the plurality of MOS FET switches, and first and second further MOS FET switches respectively connecting, through the source-drain conducting paths thereof, corresponding ones of said first and second supply terminals to said inverting input terminal of said inverter, said further MOS FET switches having said substantially common conducting resistance characteristic as said plurality of MOS FET switches, means responsive to the digital input signal for identifying the required sign of the reference voltage, and selectively applying an enabling signal to the gate terminal of the corresponding one of said further MOS FET switches thereby to enable it to conduct the reference voltage of the required sign through the source-to-drain conducting path thereof for supply to said inverting input terminal of said inverter, said inverter producing the selected reference voltage in opposite sign at its output terminal; means connecting said output terminal of said inverter to the gate terminal of each of said plurality of MOS FET switches associated with said impedance network for supply of the selected reference voltage, inverted to the respectively opposite sign, to said plurality of MOS FET switches, whereby each said reference voltage is conducted in its original sign by the corresponding further MOS FET switch and in its inverted sign by the selected MOS FET switches associated with the impedance network, thereby establishing for said reference voltages of opposite signs, a substantially common series resistance value of the sum of the first and second resistance values of said conducting MOS FET switches in the circuit from each reference voltage supply terminal to the impedance network.

Claim 5

A digital to analog converter for converting digital input signals, each including a plurality of bits, to corresponding electrical analog output signals in accordance with first and second direct current reference voltages to equal amplitude and opposite signs and utilizing MOS FET switches each including input and output terminals for connection to the source-drain conducting path thereof and a gate terminal, said switches having a substantially common characteristic of a conducting resistance of said path which varies as a function of the voltage level being switched thereby and defining first and second resistance values when switching the first and second reference voltages, respectively, and comprising: a plurality of said MOS FET switches corresponding to the plurality of bits, means for applying the digital input bit signals to the gate terminals of the corresponding MOS FET switches for selectively rendering said switches conductive, an impedance network having a plurality of input terminals connected to the output terminals of corresponding ones of said plurality of MOS FET switches for receiving the outputs thereof when the latter are rendered conductive and establishing an analog voltage therein in response to each MOS FET switch output received thereby, of a value corresponding to the digital bit position of the output and the levels of the reference signals, said network summing the analog voltages established therein in response to each digital input signal to produce a corresponding analog output signal, first and second reference voltage supply terminals at which said first and second direct current reference voltages of equal amplitude and opposite sign, respectively, are provided, means including an inverter having input and output terminals and receiving a selected one of said reference voltages at said input teRminal and producing the selected reference voltage in opposite sign at its output terminal for supply in common to the input terminals of the plurality of MOS FET switches, and first and second further MOS FET switches respectively connecting, through the source-drain conducting paths thereof, corresponding ones of said first and second supply terminals to said inverting input terminal of said inverter, said further MOS FET switches having said substantially common conducting resistance characteristic as said plurality of MOS FET switches, means responsive to the digital input signal for identifying the required sign of the reference voltage, and selectively applying an enabling signal to the gate terminal of the corresponding one of said further MOS FET switches thereby to enable it to conduct the reference voltage of the required sign through the source-to-drain conducting path thereof for supply to said inverting input terminal of said inverter, said inverter producing the selected reference voltage in opposite sign at its output terminal; means connecting said output terminal of said inverter to the gate terminal of each of said plurality of MOS FET switches associated with said impedance network for supply of the selected reference voltage, inverted to the respectively opposite sign, to said plurality of MOS FET switches, whereby each said reference voltage is conducted in its original sign by the corresponding further MOS FET switch and in its inverted sign by the selected MOS FET switches associated with the impedance network, thereby establishing for said reference voltages of opposite signs, a substantially common series resistance value of the sum of the first and second resistance values of said conducting MOS FET switches in the circuit from each reference voltage supply terminal to the impedance network.

Claim 6

A converter as recited in claim 3 wherein said plurality of MOS FET switches and said further MOS FET switch are provided in a common integrated semiconductor structure.

Claim 7

A converter as recited in claim 3 wherein said inverter comprises an operational amplifier connected at the inverting input thereof to said selecting means.

Claim 8

A converter as recited in claim 5 wherein said operational amplifier has an input resistance equal to the resistance of the impedance network for the most significant bit.

Claim 9

An inverter as recited in claim 3 wherein said impedance network includes a compensating resistor for at least the second most significant bit position, connected between the input terminal for that bit position and ground, of a value to present the same resistance to the associated MOS FET switch for that position as is presented to the MOS FET switch for the most significant bit position by the network.

Claim 10

A converter as recited in claim 3 wherein said impedance network comprises a binary resistance network.

Claim 11

A converter as recited in claim 8 wherein said binary resistance network includes resistors connected between the input terminals thereof and a common summing junction, from each of the most significant bit to the least significant bit input terminals thereof and wherein the resistors are of values R, 2R . . . 2NR from the most significant to the least significant bit positions and wherein: said binary resistance network furthermore includes a compensating resistor connected between the input terminal and ground, of a value related to the resistor for the corresponding bit position in accordance with: X (2N 1 X R/2N 1 - 1) where N is the bit position in question and X is the value of the compensating resistor, for at least the bit position of the next lesser significance than the most significant bit position.

Claim 12

A converter as recited in claim 3 wherein said impedance network comprises an R-2R resistance ladder network including a plurality of resistors of value 2R corresponding to the number of bit Positions and each 2R resistor being connected at a first terminal thereof to an input terminal of the network, and a plurality of series connected resistors of value R of adjacent ones of the resistors of value 2R, the junction of the 2R resistor for the least significant bit and the series circuit of resistors of value R being connected to ground through a resistor of value 2R and wherein: a compensating resistor of value 2R is connected between the input terminal and ground for at least the bit position of the next lesser significance than the most significant bit position.

Claim 13

A converter as recited in claim 3 wherein said impedance network comprises an R-2R resistance ladder network including a plurality of resistors of value 2R corresponding to the number of bit positions and each 2R resistor being connected at a first terminal thereof to an input terminal of the network, and a plurality of series connected resistors of value R of adjacent ones of the resistors of value 2R, the junction of the 2R resistor for the least significant bit and the series circuit of resistors of value R being connected to ground through a resistor of value 2R and wherein: a compensating resistor of a value of 10 percent of 2R is connected between the input terminal and ground for each of the most significant bit positions and at least the next less significant bit position.

Claim 14

A digital to synchro converter for generating first and second analog voltages for supply to a synchro for excitation of corresponding windings thereof to control the rotor angular position, and including first and second digital to analog converters respectively responsive to corresponding, successive digital data signal inputs, each including a plurality of bits, for generating the corresponding first and second analog control voltages in accordance with first and second reference voltages of equal amplitude and opposite signs and utilizing MOS FET switches each including input and output terminals for connection to the source-drain conducting path thereof and a gate terminal, said switches having a substantially common characteristic of a conducting resistance of said path which varies as a function of the voltage level being switched thereby and defining first and second resistance values when switching the first and second reference voltages, respectively, wherein each of said digital to analog converters comprises: a plurality of said MOS FET switches corresponding to the plurality of bits, means for applying the digital input bit signals to the gate terminals of the corresponding MOS FET switches for selectively rendering said switches conductive, an impedance network having a plurality of input terminals connected to the output terminals of corresponding ones of said plurality of MOS FET switches for receiving the outputs thereof when the latter are rendered conductive and establishing an analog voltage therein in response to each MOS FET switch output received thereby, of a value corresponding to the digital bit position of the output and the levels of the reference signals, said network summing the analog voltages established therein in response to each digital input signal to produce a corresponding analog output signal, means including an inverter having input and output terminals and receiving a selected one of said reference voltages at said input terminal and producing the selected reference voltage in opposite sign at its output terminal for supply in common to the input terminals of the plurality of MOS FET switches, first and second further MOS FET switches respectively connecting, through the source-drain conducting paths thereof, corresponding ones of said first and second supply terminals to said inverting input terminal of said inverter, said further MOS FET switches having said substantially common conducting resistance characteristic as said plurality of MOS FET switches, means responsive to the diGital input signal for identifying the required sign of the reference voltage, and selectively applying an enabling signal to the gate terminal of the corresponding one of said further MOS FET switches thereby to enable it to conduct the reference voltage of the required sign through the source-to-drain conducting path thereof for supply to said inverting input terminal of said inverter, said inverter producing the selected reference voltage in opposite sign at its output terminal; means connecting said output terminal of said inverter to the gate terminal of each of said plurality of MOS FET switches associated with said impedance network for supply of the selected reference voltage, inverted to the respectively opposite sign, to said plurality of MOS FET switches, whereby each said reference voltage is conducted in its original sign by the corresponding further MOS FET switch and in its inverted sign by the selected MOS FET switches associated with the impedance network, thereby establishing for said reference voltages of opposite signs, a substantially common series resistance value of the sum of the first and second resistance values of said conducting MOS FET switches in the circuit from each reference voltage supply terminal to the impedance network, and means for applying the first and second analog voltages from said first and second digital to analog converters to the respectively corresponding windings of the synchro.

Claim 15

A digital to synchro converter for generating first and second analog voltages for supply to a synchro for excitation of corresponding windings thereof to control the rotor angular position, and including first and second digital to analog converters respectively responsive to corresponding, successive digital data signal inputs, each including a plurality of bits, for generating the corresponding first and second analog control voltages in accordance with first and second reference voltages of equal amplitude and opposite signs and utilizing MOS FET switches each including input and output terminals for connection to the source-drain conducting path thereof and a gate terminal, said switches having a substantially common characteristic of a conducting resistance of said path which varies as a function of the voltage level being switched thereby and defining first and second resistance values when switching the first and second reference voltages, respectively, wherein each of said digital to analog converters comprises: a plurality of said MOS FET switches corresponding to the plurality of bits, means for applying the digital input bit signals to the gate terminals of the corresponding MOS FET switches for selectively rendering said switches conductive, an impedance network having a plurality of input terminals connected to the output terminals of corresponding ones of said plurality of MOS FET switches for receiving the outputs thereof when the latter are rendered conductive and establishing an analog voltage therein in response to each MOS FET switch output received thereby, of a value corresponding to the digital bit position of the output and the levels of the reference signals, said network summing the analog voltages established therein in response to each digital input signal to produce a corresponding analog output signal, means including an inverter having input and output terminals and receiving a selected one of said reference voltages at said input terminal and producing the selected reference voltage in opposite sign at its output terminal for supply in common to the input terminals of the plurality of MOS FET switches, first and second further MOS FET switches respectively connecting, through the source-drain conducting paths thereof, corresponding ones of said first and second supply terminals to said inverting input terminal of said inverter, said further MOS FET switches having said substantially common conducting resistance characteristic as said plurality of MOS FET switches, means responsive to the diGital input signal for identifying the required sign of the reference voltage, and selectively applying an enabling signal to the gate terminal of the corresponding one of said further MOS FET switches thereby to enable it to conduct the reference voltage of the required sign through the source-to-drain conducting path thereof for supply to said inverting input terminal of said inverter, said inverter producing the selected reference voltage in opposite sign at its output terminal; means connecting said output terminal of said inverter to the gate terminal of each of said plurality of MOS FET switches associated with said impedance network for supply of the selected reference voltage, inverted to the respectively opposite sign, to said plurality of MOS FET switches, whereby each said reference voltage is conducted in its original sign by the corresponding further MOS FET switch and in its inverted sign by the selected MOS FET switches associated with the impedance network, thereby establishing for said reference voltages of opposite signs, a substantially common series resistance value of the sum of the first and second resistance values of said conducting MOS FET switches in the circuit from each reference voltage supply terminal to the impedance network, and means for applying the first and second analog voltages from said first and second digital to analog converters to the respectively corresponding windings of the synchro.

Claim 16

A digital to synchro converter as recited in claim 12 wherein the MOS FET switches of each of said digital to analog converters are included in a common integrated circuit structure.