US3882484A
Expired / Lapsed
US
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Non-linear encoder and decoder
Assignee: Wescom Inc
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Filing: 1972-10-30
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Granted: 1975-05-06
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Expires: 1992-10-30
Abstract
Abstract An encoder for serially converting pulse amplitude modulated (PAM) samples into pulse code modulated (PCM) code words and a complementary decoder for serially recovering the quantized values of the samples from the code words include respective multi-stage resistive ladder attenuators which are matched, with each attenuator having several substantially independent stages, one for each weighted time slot of the PCM code word, which are assigned respective factors from a predetermined set of factors and which are selectively switched into and out of the attenuator such that the factor assigned to each stage is multiplicatively contributed to or withheld from the overall signal attenuation level afforded by the attenuator. The encoding process involves summing the sample with a reference voltage of appropriate polarity and then progressively factoring the sum by stepping the encoder attenuator in timed synchronism with the successive weighted time slots of the code words to provide a series of trial divisors which cause the encoder to generate bits with logic levels digitally indicating those of the factors that are and are not factors of the sum voltage as the sum voltage is divided to converge on the reference voltage. The decoding process, on the other hand, involves setting the decoder attenuator to provide a multiplier comprising the multiplicative combination of the factors of the sum voltage as identified by the bits of the code word, multiplying the reference voltage by the multiplier, and then subtracting the reference voltage to obtain the quantized value corresponding to the original sample. For bipolar encoding and decoding the first time slot of each code word is reserved for a sign bit and the reference voltages for the encoder and decoder are adjusted at the outset of each cycle to reflect the polarity of the sample. Appropriate selection of the reference voltage magnitude and of the factors comprised by the encoder and decoder attenuators provides complementary non-linear encoding and decoding in accordance with a known companding function of proven effectivity for maintaining a relatively high signal-to-distortion ratio with only a relatively few time slots alotted each PCM code word.
Inventors
- 👤 Adrian Paul Brokaw
- 👤 Daniel Y S Chin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 06:35
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38; H03M1/40; H03M1/66; H03M1/667
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
8 words
first bistable means coupled to said supply means,
Claim 2
Dependent Claim
8 words
first bistable means coupled to said supply means,
Claim 3
Dependent Claim
16 words
an attenuator means having a plurality of substantially independent stages associated with respective attenuator factors, and
Claim 4
Dependent Claim
16 words
an attenuator means having a plurality of substantially independent stages associated with respective attenuator factors, and
Claim 5
Dependent Claim
271 words
An encoder for converting an analog signal sample v1, into a pulse code modulated code word v0, said encoder having a plurality of possible code steps for encoding signal samples of a given polarity and comprising the combination of a. an input means coupled to receive said sample, b. a supply means for providing a reference voltage having a predetermined magnitude of V1C1/ Mu , where V1 is a predetermined overload value of the sample v1, Mu is a predetermined companding constant, and C1 is another predetermined constant; c. means coupled to said input means and said supply means for summing said sample with said reference voltage to obtain a sum voltage having an unknown magnitude of (V1C1/ Mu + v1), said means including attenuator means having an attenuation level incrementally adjustable in accordance with a function (C2+ Mu ) /m, where C2 is a predetermined constant, Alpha is an adjustable variable equal to any one of said code stepS, and m is a predetermined code step provided for the overload sample value V1; d. comparator means coupled to said attenuator means for comparing the sum voltage as attenuated by said atenuator means against a decision point voltage having a predetermined magnitude of (V1C1/ Mu - Delta v), where Delta v is a predetermined offset voltage, to provide an output signal having a polarity dependent on the magnitude of the attenuated sum voltage relative to the magnitude of said decision point voltage; e. logic means responsive to the polarity of said output signal and coupled to said attenuator means for successively adjusting Alpha to approach n in accordance with the function
Claim 6
Dependent Claim
271 words
An encoder for converting an analog signal sample v1, into a pulse code modulated code word v0, said encoder having a plurality of possible code steps for encoding signal samples of a given polarity and comprising the combination of a. an input means coupled to receive said sample, b. a supply means for providing a reference voltage having a predetermined magnitude of V1C1/ Mu , where V1 is a predetermined overload value of the sample v1, Mu is a predetermined companding constant, and C1 is another predetermined constant; c. means coupled to said input means and said supply means for summing said sample with said reference voltage to obtain a sum voltage having an unknown magnitude of (V1C1/ Mu + v1), said means including attenuator means having an attenuation level incrementally adjustable in accordance with a function (C2+ Mu ) /m, where C2 is a predetermined constant, Alpha is an adjustable variable equal to any one of said code stepS, and m is a predetermined code step provided for the overload sample value V1; d. comparator means coupled to said attenuator means for comparing the sum voltage as attenuated by said atenuator means against a decision point voltage having a predetermined magnitude of (V1C1/ Mu - Delta v), where Delta v is a predetermined offset voltage, to provide an output signal having a polarity dependent on the magnitude of the attenuated sum voltage relative to the magnitude of said decision point voltage; e. logic means responsive to the polarity of said output signal and coupled to said attenuator means for successively adjusting Alpha to approach n in accordance with the function
Claim 7
Dependent Claim
98 words
switch means coupled to said stages for switching said stages into and out of said attenuator means, whereby said attenuator means has an attenuation level incrementally adjustable from substantially zero to a higher predetermined limit; d. comparator means coupled to said attenuator means for comparing the magnitude of said sum voltage against the magnitude of a predetermined decision point voltage to provide an output signal having a polarity dependent on the magnitude of the attenuated sum voltage relative to the magnitude of said decision point voltage; e. logic means for cycling said encoder at said repetition rate including
Claim 8
Dependent Claim
98 words
switch means coupled to said stages for switching said stages into and out of said attenuator means, whereby said attenuator means has an attenuation level incrementally adjustable from substantially zero to a higher predetermined limit; d. comparator means coupled to said attenuator means for comparing the magnitude of said sum voltage against the magnitude of a predetermined decision point voltage to provide an output signal having a polarity dependent on the magnitude of the attenuated sum voltage relative to the magnitude of said decision point voltage; e. logic means for cycling said encoder at said repetition rate including
Claim 9
Dependent Claim
60 words
The encoder of claim 1 wherein said bits comprise the bits for the weighted time slots of the code word v0, whereby said code word provides a digital representation of a divisor (C2 + Mu ) n/m for dividing the sum voltage (V1C1/ Mu + v1) to cause the divided sum voltage to approximate the reference voltage V1C1/ Mu .
Claim 10
Dependent Claim
8 words
second bistable means coupled to said switch means,
Claim 11
Dependent Claim
8 words
second bistable means coupled to said switch means,
Claim 12
Dependent Claim
53 words
means coupled to said first and second bistable means for switching said bistable means to a first state in preparation for each encoding cycle, whereby said stages are then all removed from said attenuator means to reduce the attenuation level thereof to substantially zero and said reference voltage then has a predetermined polarity,
Claim 13
Dependent Claim
53 words
means coupled to said first and second bistable means for switching said bistable means to a first state in preparation for each encoding cycle, whereby said stages are then all removed from said attenuator means to reduce the attenuation level thereof to substantially zero and said reference voltage then has a predetermined polarity,
Claim 14
Dependent Claim
18 words
The encoder of claim 2 where the constant C1 and C2 are selected to have values of unity.
Claim 15
Dependent Claim
25 words
The encoder of claim 3 wherein said comparator means comprises an open loop operational amplifier to virtually preclude said output signal from stabilizing at zero.
Claim 16
Dependent Claim
26 words
clock means for advancing said encoder at a predetermined digital bit rate to thereby divide such encoding cycle into a plurality of equal length time slots,
Claim 17
Dependent Claim
26 words
clock means for advancing said encoder at a predetermined digital bit rate to thereby divide such encoding cycle into a plurality of equal length time slots,
Claim 18
Dependent Claim
39 words
means coupled to said comparator means and controlled by said clock means for outputting respective bits into said time slots, with said bits having logic levels dependent on the polarity of said output signal on a time slot-by-slot basis,
Claim 19
Dependent Claim
39 words
means coupled to said comparator means and controlled by said clock means for outputting respective bits into said time slots, with said bits having logic levels dependent on the polarity of said output signal on a time slot-by-slot basis,
Claim 20
Dependent Claim
73 words
The encoder of claim 4 wherein said attenuator means comprises a plurality of substantially independent attenuation factors logarithmically weighted in accordance with the function (1 + Mu ) /m, where Alpha has successive binary values for the respective attenuation factors, and said logic means include means for switching said factors into and out of said attenuator means to thereby adjust the attenuation level of said attenuator to approach (1 + Mu ) n/m.
Claim 21
Dependent Claim
70 words
The encoder of claim 5 wherein said attenuator means includes a plurality of substantially independent stages each assigned a respective one of said attenuation factors, and respective switch means coupled to said stages whereby each of said stages may be switched into and out of said attenuator means to multiplicatively contribute and withhold, respectively, the attenuation factor assigned to said stage to and from the attenuation level of said attenuator.
Claim 22
Dependent Claim
64 words
means coupled between said comparator means and said first bistable means to switch said bistable means to a second state to thereby reverse the polarity of said reference voltage only if the polarity of said output signal during the first time slot of an encoding cycle is consistent with said decision point voltage having a greater magnitude at that time than said sum voltage;
Claim 23
Dependent Claim
64 words
means coupled between said comparator means and said first bistable means to switch said bistable means to a second state to thereby reverse the polarity of said reference voltage only if the polarity of said output signal during the first time slot of an encoding cycle is consistent with said decision point voltage having a greater magnitude at that time than said sum voltage;
Claim 24
Dependent Claim
41 words
means coupled between said clock means and said second bistable means for sequentially switching said stages into said attenuator means at said digital bit rate and beginning as the encoder advances to the second time slot of each encoding cycle, and
Claim 25
Dependent Claim
41 words
means coupled between said clock means and said second bistable means for sequentially switching said stages into said attenuator means at said digital bit rate and beginning as the encoder advances to the second time slot of each encoding cycle, and
Claim 26
Dependent Claim
83 words
The encoder of claim 6 wherein said factors are switched into said attenuator means in declining order of significance at a predetermined digital bit rate, and said logic means further includes means responsive to the polarity of said output signal for selectively switching any but the least significant one of said factors out of said attenuator whenever the attenuation level of said attenuator is increased to a level greater than (1 + Mu ) n/m by switching said one factor into said attenuator.
Claim 27
Dependent Claim
113 words
The encoder of claim 1 wherein said offset voltage has a value of zero so that the magnitude of said decision point voltage equals the magnitude of said reference voltage, said comparator means comprises an open loop operational amplifier to thereby virtually preclude said output signal from stabilizing at zero, said attenuator means includes a plurality of substantially independent attenuation factOrs logarithmically weighted to correspond to the function (C2 + Mu ) /m for respective ones of successive values of Alpha , and said logic means includes means for switching said factors into and out of said attenuation means to thereby adjust the attenuation level thereof to approach (C2 + Mu ) n/m.
Claim 28
Dependent Claim
59 words
means coupled between said comparator means and said bistable means enabled at any time, other than after the encoder has advanced to the final time slot of a cycle, the magnitude of said sum voltage drops below the magnitude of said decision point voltage to selectively switch the most recently inserted of said stages out of said attenuator means.
Claim 29
Dependent Claim
59 words
means coupled between said comparator means and said bistable means enabled at any time, other than after the encoder has advanced to the final time slot of a cycle, the magnitude of said sum voltage drops below the magnitude of said decision point voltage to selectively switch the most recently inserted of said stages out of said attenuator means.
Claim 30
Dependent Claim
154 words
The encoder of claim 8 wherein said attenuator means includes a plurality of substantially independent stages each assigned a respective one of said factors, and respective switch means coupled to said stages whereby each of said stages may be switched into and out of said attenuator means to multiplicatively contribute or withhold, respectively, the factor assigned thereto to and from the overall attenuation level of said attenuator; and said logic means includes a register for supplying control signals for said switch means to switch said stages into said attenuator means in a predetermined order, and means coupled between said comparator means and said register for selectively signaling said register whenever the attenuation level of said attenuator means exceeds (C2 + Mu ) n/m so that said register then supplies a further control signal for said switch means to selectively switch out of said attenuation means the stage most recently switched into said attenuator means.
Claim 31
Dependent Claim
30 words
The encoder of claim 9 wherein said order is selected so that said attenuation factors are multiplicatively contributed to the attenuation level of said attenuator in declining order of significance.
Claim 32
Dependent Claim
134 words
The encoder of claim 1 wherein said attenuator means includes a plurality of substantially independent attenuation factors logarithmically weighted to correspond to the function (C2+ Mu ) m for respective values of Alpha , said offset voltage has a value substantially equal to one-half the voltage value of that portion of the input sample corresponding to the least significant of said attenuation factors so that the magnitude of said decision point voltage is offset from the magnitude of said reference voltage, said comparator means includes an open loop operational amplifier to thereby virtually preclude said output signal from stabilizing at zero, and said logic means includes means for switching said factors into and out of said attenuator means to thereby adjust the attenuation level of said attenuator means to approach (C2+ Mu ) n/m.
Claim 33
Dependent Claim
154 words
The encoder of claim 11 wherein said attenuator means includes a plurality of substantially independent stages each assigned a respective one of said factors, and respective switch means coupled to said stages whereby each of said stages may be switched into and out of said attenuator means to multiplicatively contribute or withhold, respectively, the factor assigned thereto to and from the overall attenuation level of said attenuator; and said logic means includes a register for supplying control signals for said switch means to switch said stages into said attenuator means in a predetermined order, and means coupled between said comparator means and said register for selectively signaling said register whenever the attenuation level of said attenuator means exceeds (C2 + Mu ) n/m so that said register then supplies a further control signal for said switch means to selectively switch out of said attenuation means the stage most recently switched into said attenuator means.
Claim 34
Dependent Claim
30 words
The encoder of claim 12 wherein said order is selected so that said attenuation factors are multiplicatively contributed to the attenuation level of said attenuator in declining order of significance.
Claim 35
Dependent Claim
94 words
An encoder for generating a train of pulse code modulated code words in response to a series of bipolar analog signal samples having a predetermined repetition rate, said encoder comprising the combination of a. input means coupled to serially receive said samples; b. a reversible polarity supply means for Providing a reference voltage having a predetermined magnitude; c. means coupled to said input means and said supply means for summing each of said samples with said reference voltage to thereby obtain for each sample a sum voltage having an unknown magnitude, said means including
Claim 36
Dependent Claim
94 words
An encoder for generating a train of pulse code modulated code words in response to a series of bipolar analog signal samples having a predetermined repetition rate, said encoder comprising the combination of a. input means coupled to serially receive said samples; b. a reversible polarity supply means for Providing a reference voltage having a predetermined magnitude; c. means coupled to said input means and said supply means for summing each of said samples with said reference voltage to thereby obtain for each sample a sum voltage having an unknown magnitude, said means including
Claim 37
Dependent Claim
231 words
The encoder of claim 14 wherein said reference voltage is selected to equal V1C1/ Mu , where V1 is a predetermined overload input signal which follows the polarities of the samples v1, Mu is a predetermined companding constant, and C1 is another predetermined constant, whereby the sum voltage for each sample has a magnitude of (V1C1/ Mu + v1) at least as the encoding cycle advances to the second of said time slots; the factors assigned to said attenuator stages are logarithmically weighted to correspond to the function (C2 + Mu ) /m for respective values of Alpha , where C2 is another predetermined constant, Alpha is an adjustable variable defining any one of the code steps available for encoding samples of a given polarity, and m is the code step corresponding to the input overload signal V1; and the magnitude of said decision point voltage is selected to substantially equal (V1C1/ Mu - Delta v), where Delta v represents any offset between the magnitude of said reference voltage and the magnitude of the decision point voltage; whereby each code word includes a bit having a logic level digitally representing the polarity of the applied sample v1, followed by a plurality of bits having logic levels digitally representing, in factored form, a divisor approaching (C2 + Mu ) n/m where n is the code step corresponding to the applied sample v1.
Claim 38
Dependent Claim
15 words
The encoder of claim 15 where C1 and C2 are both selected to equal unity.
Claim 39
Dependent Claim
71 words
The encoder of claim 16 wherein Delta v is selected to equal zero, said comparator means includes an open loop operational amplifier to virtually preclude said output signal from stabilizing at zero, and said attenuator stages are switched into said attenuator means in a predetermined order starting with the stages assigned the most significant of said factors and proceeding in order to the stage assigned the least significant of said factors.
Claim 40
Dependent Claim
89 words
The encoder of claim 16 wherein Delta v is selected to equal one-half the voltage value of that portion of the input sample corresponding to the least significant of said factors, said comparator means includes an open loop operational amplifier to virtually preclude said output signal from stabilizing at zero, and said attenuator stages are switched into said attenuator means in a predetermined order starting with the stages assigned the most significant of said factors and preceeding in order to the stage assigned the least significant of said factors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-05 | 1978-11-04 | 1979-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-05 | 1982-11-04 | 1983-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-05 | 1986-11-04 | 1987-05-06 | $7700.00 | Window Closed / Lapsed |