Patent US4266145A successfully refreshed from Google Patents.
US4266145A
Expired / Lapsed
US
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Time dependent master reset
Assignee: NCR Voyix Corp
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Filing: 1979-05-09
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Granted: 1981-05-05
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Expires: 1999-05-09
Abstract
Abstract A circuit for use with logic circuitry preventing any transients due to the power down and power up conditions of a power supply from causing any false or random operations of the logic. The turn off transients are suppressed by a reset signal to the logic circuitry generated by a timing module which is triggered when it detects an absence of AC signal over a specified period of time and is then held in a reset mode until the power supply voltage completely decays. The turn on transients are suppressed by a reset signal to the logic circuitry generated by the timing module, which is held in a reset mode until the power supply voltage has stabilized.
Inventors
- 👤 Gene L. Amacher
- 👤 Wesley D. Dickover
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 18:52
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22; H02; H02H; H02H3/00; H02H3/24; H02H3/247; H03K17/16; H03K2017/226
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
115 words
A circuit for protecting logic circuitry from transients caused by the decay of a power supply, comprising: first circuit means for generating a first signal upon detecting the absence of an AC signal from said power supply; second circuit means, responsive to said first signal, for generating a second signal upon said first signal reaching a predetermined voltage condition; third circuit means, coupled to said second circuit means, for generating a third signal upon generation of said second signal for use in protecting said logic circuitry; and fourth circuit means, coupled to said second and third circuit means, for maintaining said second and third signals until said power supply voltage decays to a predetermined level.
Claim 2
Dependent Claim
115 words
A circuit for protecting logic circuitry from transients caused by the decay of a power supply, comprising: first circuit means for generating a first signal upon detecting the absence of an AC signal from said power supply; second circuit means, responsive to said first signal, for generating a second signal upon said first signal reaching a predetermined voltage condition; third circuit means, coupled to said second circuit means, for generating a third signal upon generation of said second signal for use in protecting said logic circuitry; and fourth circuit means, coupled to said second and third circuit means, for maintaining said second and third signals until said power supply voltage decays to a predetermined level.
Claim 3
Dependent Claim
20 words
The circuit of claim 1, wherein said predetermined voltage level of said first signal is controlled by a resistor-capacitor network.
Claim 4
Dependent Claim
14 words
The circuit of claim 2, wherein said second circuit means comprises a precision timer.
Claim 5
Dependent Claim
25 words
The circuit of claim 3, wherein said first circuit means includes sensing means for detecting the absence of an AC signal from said power supply.
Claim 6
Dependent Claim
23 words
The circuit of claim 3, wherein said third circuit means includes first switching means for applying said third signal to said logic circuitry.
Claim 7
Dependent Claim
21 words
The circuit of claim 5, wherein said fourth circuit means includes second switching means for maintaining said second and third signals.
Claim 8
Dependent Claim
18 words
The circuit of claim 6, wherein said sensing means and said first and second switching means comprise transistors.
Claim 9
Dependent Claim
112 words
A circuit for protecting logic circuitry from transients caused by the generation of a power supply, comprising: first circuit means for generating a first signal for a predetermined time upon the generation of said power supply; second circuit means, coupled to said first circuit means, for generating a second signal in response to said first signal; third circuit means, coupled to said second circuit means and responsive to said second signal, for generating a third signal for use in protecting said logic circuitry until said first signal subsides; and fourth circuit means, coupled to said first and third circuit means, for stabilizing said first circuit means after said first signal has subsided.
Claim 10
Dependent Claim
112 words
A circuit for protecting logic circuitry from transients caused by the generation of a power supply, comprising: first circuit means for generating a first signal for a predetermined time upon the generation of said power supply; second circuit means, coupled to said first circuit means, for generating a second signal in response to said first signal; third circuit means, coupled to said second circuit means and responsive to said second signal, for generating a third signal for use in protecting said logic circuitry until said first signal subsides; and fourth circuit means, coupled to said first and third circuit means, for stabilizing said first circuit means after said first signal has subsided.
Claim 11
Dependent Claim
14 words
The circuit of claim 8, wherein said predetermined time is controlled by a capacitor.
Claim 12
Dependent Claim
14 words
The circuit of claim 9, wherein said second circuit means comprises a precision timer.
Claim 13
Dependent Claim
23 words
The circuit of claim 10, wherein said third circuit means includes first switching means for applying said third signal to said logic circuitry.
Claim 14
Dependent Claim
20 words
The circuit of claim 11, wherein said fourth circuit means includes second switching means for stabilizing said first circuit means.
Claim 15
Dependent Claim
14 words
The circuit of claim 12, wherein said first and second switching means comprise transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-05-04 | 1984-11-03 | 1985-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-05-04 | 1988-11-03 | 1989-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-05-04 | 1992-11-03 | 1993-05-05 | $7700.00 | Window Closed / Lapsed |