Patent US4266099A successfully refreshed from Google Patents.
US4266099A
Expired / Lapsed
US
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Pulse rejection and duration correction circuit
Assignee: Nortel Networks Ltd
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Filing: 1979-05-29
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Granted: 1981-05-05
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Expires: 1999-05-29
Abstract
Abstract A circuit which is particularly adapted for reconstructing fixed time duration dialing pulses in a telephone communications system while rejecting spurious pulses of less than a selected pulse duration. The circuit utilizes two coupling networks having integrated outputs of opposite polarity which are summed after passing through two separate switching amplifiers. The summed outputs are fed through a third switching amplifier having a hysteresis characteristic so that it switches only when both outputs have switched to the same polarity.
Inventors
- 👤 Inanc Kayalioglu
- 👤 Vincent G. Roman
- 👤 Ted J. Lewandowski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:40
CPC Classifications
H; H04; H04Q; H04Q1/00; H04Q1/18; H04Q1/30; H04Q1/32; H04Q1/36
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
145 words
A pulse rejection circuit comprising: a circuit input and a circuit output; first, second and third switching amplifiers, each having an input and an output; a first coupling network having a direct coupled output for positive polarity signals and an integrated coupled output for negative polarity signals, connected between the input of the circuit and the input of the first amplifier; a second coupling network having a direct coupled output for negative polarity signals and and integrated coupled output for positive polarity signals, connected between the input of the circuit and the input of the second amplifier; a summing network for connecting the summed outputs of the first and second amplifiers to the input of the third amplifier, the third amplifier having a switching hystersis so that it switches only when both outputs of the first and second amplifiers have switched to the same polarity.
Claim 2
Dependent Claim
145 words
A pulse rejection circuit comprising: a circuit input and a circuit output; first, second and third switching amplifiers, each having an input and an output; a first coupling network having a direct coupled output for positive polarity signals and an integrated coupled output for negative polarity signals, connected between the input of the circuit and the input of the first amplifier; a second coupling network having a direct coupled output for negative polarity signals and and integrated coupled output for positive polarity signals, connected between the input of the circuit and the input of the second amplifier; a summing network for connecting the summed outputs of the first and second amplifiers to the input of the third amplifier, the third amplifier having a switching hystersis so that it switches only when both outputs of the first and second amplifiers have switched to the same polarity.
Claim 3
Dependent Claim
180 words
A pulse rejection and duration correction circuit comprising: a circuit input and a circuit output; first and second operational amplifiers each having first and second inputs inverted with respect to each other, and an output; a first coupling network having a direct coupled output for positive polarity signals and an integrated coupled output for negative polarity signals, connected between the circuit input and the first input to the first amplifier; a second coupling network having a direct coupled output for negative polarity signals and an integrated coupled output for positive polarity signals, connected between the circuit input and the first input to the second amplifier; integrating network means connected between the circuit input and each of the second inputs to the first and second amplifiers; a summing network for connecting the outputs of the first and second amplifiers to an input of a third operational amplifier, the third operational amplifier including feedback means to provide a switching hystersis, so that the third amplifier switches only when both outputs of the first and second amplifiers have switched to the same polarity.
Claim 4
Dependent Claim
180 words
A pulse rejection and duration correction circuit comprising: a circuit input and a circuit output; first and second operational amplifiers each having first and second inputs inverted with respect to each other, and an output; a first coupling network having a direct coupled output for positive polarity signals and an integrated coupled output for negative polarity signals, connected between the circuit input and the first input to the first amplifier; a second coupling network having a direct coupled output for negative polarity signals and an integrated coupled output for positive polarity signals, connected between the circuit input and the first input to the second amplifier; integrating network means connected between the circuit input and each of the second inputs to the first and second amplifiers; a summing network for connecting the outputs of the first and second amplifiers to an input of a third operational amplifier, the third operational amplifier including feedback means to provide a switching hystersis, so that the third amplifier switches only when both outputs of the first and second amplifiers have switched to the same polarity.
Claim 5
Dependent Claim
143 words
A pulse rejection and duration correction circuit as defined in claim 2 in which each coupling network includes a shunt connected diode and resistor connected in series between the circuit input and the respective first input to the operational amplifier, and a capacitor connected between the respective first input to the operational amplifier and a common reference connection; in which the integrating network includes a resistor connected in series between the circuit input and the second inputs to the first and second amplifiers and a shunt connected resistor and capacitor connected between the second inputs and the common reference connections; in which the summing network includes separate resistors connected between each output of the first and second operational amplifiers and the input to the third amplifier; and in which the third operational amplifier has a positive feedback resistor to provide the switching hystersis.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-05-04 | 1984-11-03 | 1985-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-05-04 | 1988-11-03 | 1989-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-05-04 | 1992-11-03 | 1993-05-05 | $7700.00 | Window Closed / Lapsed |