Patent US4260906A successfully refreshed from Google Patents.
US4260906A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device and logic circuit constituted by the semiconductor device
Assignee: Toshiba Corp
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Filing: 1978-05-15
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Granted: 1981-04-07
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Expires: 1998-05-15
Abstract
Abstract A semiconductor device comprises a P type semiconductor substrate; an N type layer buried in the P type substrate; and an N type isolating region extending from the surface of the P type substrate to the N type buried region to provide a P type isolated region in the P type substrate. In the P type isolated region marked off by the N type isolating region is formed a first N type region so as not to contact the N type isolating region and buried region and a P type second region is diffused in the first N type region. A logic circuit is constituted by a first vertical PNP transistor formed of the P type second region, first N type region and P type isolated region and a second vertical NPN transistor formed of the first N type region, P type isolated region and N type buried region.
Inventors
- 👤 Yukuya Tokumaru
- 👤 Masanori Nakai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:47
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/084; H03K19/091; H10; H10D; H10D84/00; H10D84/60; H10D84/65; H10D84/652; Y; Y10; Y10S; Y10S148/00; Y10S148/087; Y10S148/088; Y10S148/139
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
240 words
An integrated injector logic semiconductor device having at least one input terminal and at least one output terminal, which comprises a semiconductor substrate of one conductivity type; at least one region buried in the semiconductor substrate with the opposite conductivity type thereto; an isolating region formed in the semiconductor substrate with the opposite conductivity type thereto and extending from said surface of the semiconductor substrate into said buried region to form at least one isolated region with the same conductivity type as the semiconductor substrate, said isolating region and isolated region being connected to said output terminal and input terminal respectively; a first region formed in the isolated region with the opposite conductivity type to the semiconductor substrate to be uncontacted with the buried region and isolating region, said first region including a main region and an auxiliary region in contact with said main region and at a higher impurity concentration than said main region; and a second region formed in the main region of said first region with the same conductivity type as the semiconductor substrate, whereby a first vertical transistor of one polarity is constituted by said second region, said first region and said isolated region acting as emitter, base and collector, respectively, said emitter and base being forwardly biased and a second vertical transistor of opposite polarity is constituted by said first region, said isolated region and said buried region acting as emitter, base and collector respectively.
Claim 2
Dependent Claim
240 words
An integrated injector logic semiconductor device having at least one input terminal and at least one output terminal, which comprises a semiconductor substrate of one conductivity type; at least one region buried in the semiconductor substrate with the opposite conductivity type thereto; an isolating region formed in the semiconductor substrate with the opposite conductivity type thereto and extending from said surface of the semiconductor substrate into said buried region to form at least one isolated region with the same conductivity type as the semiconductor substrate, said isolating region and isolated region being connected to said output terminal and input terminal respectively; a first region formed in the isolated region with the opposite conductivity type to the semiconductor substrate to be uncontacted with the buried region and isolating region, said first region including a main region and an auxiliary region in contact with said main region and at a higher impurity concentration than said main region; and a second region formed in the main region of said first region with the same conductivity type as the semiconductor substrate, whereby a first vertical transistor of one polarity is constituted by said second region, said first region and said isolated region acting as emitter, base and collector, respectively, said emitter and base being forwardly biased and a second vertical transistor of opposite polarity is constituted by said first region, said isolated region and said buried region acting as emitter, base and collector respectively.
Claim 3
Dependent Claim
32 words
A semiconductor device according to claim 1, wherein an ohmic contact region is formed in the isolated region and the isolated region is connected to said input terminal through said ohmic region.
Claim 4
Dependent Claim
51 words
A semiconductor device according to claim 1, wherein at least one metal layer is formed on the isolated region marked off by the isolating region to form at least one Schottky diode at the junction of the metal layer and isolated region, said metal layer being connected to said input terminal.
Claim 5
Dependent Claim
60 words
A semiconductor device according to claim 1 having a plurality of input terminals, wherein a plurality of metal layers connected to said input terminals are formed on the isolated region marked off by the isolating region to provide an AND gate circuit comprising a plurality of Schottky diodes formed at the junctions of the metal layers and the isolated region.
Claim 6
Dependent Claim
115 words
A semiconductor device according to claim 1, wherein at least one first metal layer is formed on the surface of the isolated region marked off by the isolating region to form at least one first Schottky diode at the first junction of the first metal layer and isolated region, and a second metal layer is formed on the surface of the isolating region to provide a second Schottky diode at the second junction of the second metal layer and isolating region, said first metal layer being connected to the input terminal and said second layer being connected to the isolated region whereby the second Schottky diode acts as a clamping diode for the second transistor.
Claim 7
Dependent Claim
123 words
A semiconductor device according to claim 1 having a plurality of input terminals wherein a plurality of first metal layers are formed on the surface of the isolated region marked off by the isolating region to form a first Schottky diode at the first junction of each of the first metal layers and isolated region and a second metal layer is formed on the surface of the isolating region to provide a second Schottky diode at the second junction of the second metal layer and isolating region, said first metal layers being connected to the input terminals respectively, and said second metal layer being connected to the isolated region whereby the second Schottky diode acts as a clamping diode for the second transistor.
Claim 8
Dependent Claim
35 words
A semiconductor device according to claim 5 or 6 wherein said first and second junctions have the same area and said first metal layer is made of titanium while said second metal layer of platinum.
Claim 9
Dependent Claim
37 words
A semiconductor device according to claim 5 or 6 wherein an ohmic contact region is formed adjacent to the isolating region and the second metal layer is formed on both the isolating region and ohmic contact region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-04-06 | 1984-10-06 | 1985-04-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-04-06 | 1988-10-06 | 1989-04-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-04-06 | 1992-10-06 | 1993-04-07 | $7700.00 | Window Closed / Lapsed |