Patent US4259738A successfully refreshed from Google Patents.
US4259738A
Expired / Lapsed
US
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Multiplexer system providing improved bit count integrity
Assignee: Raytheon Co
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Filing: 1979-05-18
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Granted: 1981-03-31
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Expires: 1999-05-18
Abstract
Abstract A multiplexer system providing a transmission frame field containing information derived from the cumulative total of stuff bits used over a plurality of frames. The stuff bits which also have assigned positions in the transmission frame are generally used in asynchronous systems to compensate for the input data rate of a group not being a fixed submultiple of the transmission rate. The demultiplexer system uses the information derived from the cumulative total to improve the bit count integrity performance of data channeled out to a user device. Also, during transmission fade conditions, the demultiplexer uses information derived from the frequency of past stuff operations to maintain group bit count close to its expected value.
Inventors
- 👤 Nathan A. Liskov
- 👤 David L. Hendry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:29
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0079; H04L7/0083; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/07; H04L25/00; H04L25/02; H04L25/05; H04L7/04; H04L7/041; H04L2007/045
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
167 words
In combination: means for transferring digital bits from a first serial digital data stream to assigned bit positions in a predetermined time interval of a second higher rate serial digital data stream, said bit positions being assigned for bits in addition to a predetermined number of bits of said first data stream always transferred during a predetermined time interval; said transferring means comprising means responsive to the data rate of said first data stream with respect to the data rate of said second data stream for controlling the number of bits transferred into said bit positions; means for providing a number derived from the number of bits transferred to said bit positions during a plurality of said predetermined time intervals; means for deriving said first serial data stream from said second data stream comprising means responsive to said derived number for maintaining bit count integrity of said first serial data stream; and said maintaining means comprising means for predicting an expected number based on previous derived numbers.
Claim 2
Dependent Claim
167 words
In combination: means for transferring digital bits from a first serial digital data stream to assigned bit positions in a predetermined time interval of a second higher rate serial digital data stream, said bit positions being assigned for bits in addition to a predetermined number of bits of said first data stream always transferred during a predetermined time interval; said transferring means comprising means responsive to the data rate of said first data stream with respect to the data rate of said second data stream for controlling the number of bits transferred into said bit positions; means for providing a number derived from the number of bits transferred to said bit positions during a plurality of said predetermined time intervals; means for deriving said first serial data stream from said second data stream comprising means responsive to said derived number for maintaining bit count integrity of said first serial data stream; and said maintaining means comprising means for predicting an expected number based on previous derived numbers.
Claim 3
Dependent Claim
14 words
The combination in accordance with claim 1 wherein said transferring means comprises a selector.
Claim 4
Dependent Claim
16 words
The combination in accordance with claim 2 wherein said control means comprises a read only memory.
Claim 5
Dependent Claim
16 words
The combination in accordance with claim 3 wherein said control means further comprises an up/down counter.
Claim 6
Dependent Claim
14 words
The combination in accordance with claim 4 wherein said providing means comprises a counter.
Claim 7
Dependent Claim
174 words
A multiplexer system comprising in combination: means for storing digital bits from a first serial digital data stream; means for transferring bits from said storing means to assigned bit positions in a second higher rate serial data stream, said bit positions being assigned for bits in addition to a predetermined number of bits from said storing means always transferred during a predetermined time interval; said transferring means comprising means for controlling the number of said bits transferred to said bit positions during a predetermined time interval; said control means being responsive to the number of said bits stored in said storing means; means for providing a number derived from the number of said bits transferred to said bit positions during a plurality of said predetermined time intervals; means for deriving said first serial data stream from said second data stream comprising means responsive to said derived number for maintaining bit count integrity of said first serial data stream; and said maintaining means comprising means for predicting an expected number based on previous derived numbers.
Claim 8
Dependent Claim
174 words
A multiplexer system comprising in combination: means for storing digital bits from a first serial digital data stream; means for transferring bits from said storing means to assigned bit positions in a second higher rate serial data stream, said bit positions being assigned for bits in addition to a predetermined number of bits from said storing means always transferred during a predetermined time interval; said transferring means comprising means for controlling the number of said bits transferred to said bit positions during a predetermined time interval; said control means being responsive to the number of said bits stored in said storing means; means for providing a number derived from the number of said bits transferred to said bit positions during a plurality of said predetermined time intervals; means for deriving said first serial data stream from said second data stream comprising means responsive to said derived number for maintaining bit count integrity of said first serial data stream; and said maintaining means comprising means for predicting an expected number based on previous derived numbers.
Claim 9
Dependent Claim
16 words
The combination in accordance with claim 6 wherein said storing means comprises a first-in, first-out memory.
Claim 10
Dependent Claim
14 words
The combination in accordance with claim 7 wherein said transferring means comprises a selector.
Claim 11
Dependent Claim
207 words
An asynchronous multiplexer-demultiplexer system providing improved bit count integrity and comprising in combination: first storing means for storing digital bits from a first serial digital data stream; means for transferring said bits from said first storing means to bit positions in a second higher rate serial digital data stream, said bit positions being assigned for bits in addition to a predetermined number of said bits always transferred during a predetermined time interval; said transferring means comprising means for controlling the number of bits transferred to said bit positions; said control means being responsive to the number of said bits stored in said first storing means; means for providing a number derived from the number of said bits transferred to said bit positions during a plurality of said predetermined time intervals; second storing means for storing said derived number; said transferring means comprising means for transferring said derived number from said second storing means to said second serial digital data stream; means for providing said first serial digital data bits from said second serial digital data stream to an output channel; and means responsive to said derived number for maintaining bit count integrity to said channel comprising means for predicting an expected number based on previous derived numbers.
Claim 12
Dependent Claim
207 words
An asynchronous multiplexer-demultiplexer system providing improved bit count integrity and comprising in combination: first storing means for storing digital bits from a first serial digital data stream; means for transferring said bits from said first storing means to bit positions in a second higher rate serial digital data stream, said bit positions being assigned for bits in addition to a predetermined number of said bits always transferred during a predetermined time interval; said transferring means comprising means for controlling the number of bits transferred to said bit positions; said control means being responsive to the number of said bits stored in said first storing means; means for providing a number derived from the number of said bits transferred to said bit positions during a plurality of said predetermined time intervals; second storing means for storing said derived number; said transferring means comprising means for transferring said derived number from said second storing means to said second serial digital data stream; means for providing said first serial digital data bits from said second serial digital data stream to an output channel; and means responsive to said derived number for maintaining bit count integrity to said channel comprising means for predicting an expected number based on previous derived numbers.
Claim 13
Dependent Claim
34 words
The combination in accordance with claim 9 wherein said maintaining means comprises means responsive to said expected number for determining the number of data bits provided to said output channel during a transmission fade.
Claim 14
Dependent Claim
17 words
The combination in accordance with claim 10 wherein said first storing means comprises a first-in, first-out memory.
Claim 15
Dependent Claim
14 words
The combination in accordance with claim 11 wherein said transferring means comprises a selector.
Claim 16
Dependent Claim
16 words
The combination in accordance with claim 12 wherein said controlling means comprises a read only memory.
Claim 17
Dependent Claim
16 words
The combination in accordance with claim 13 wherein said control means further comprises an up/down counter.
Claim 18
Dependent Claim
16 words
The combination in accordance with claim 14 wherein said second storing means comprises an up/down counter.
Claim 19
Dependent Claim
14 words
The combination in accordance with claim 15 wherein said determining means comprises a microprocessor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-03-30 | 1984-09-29 | 1985-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-03-30 | 1988-09-29 | 1989-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-03-30 | 1992-09-29 | 1993-03-31 | $7700.00 | Window Closed / Lapsed |