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US4257832A
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Process for producing an integrated multi-layer insulator memory cell
Assignee: Siemens AG
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Filing: 1979-07-18
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Granted: 1981-03-24
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Expires: 1999-07-18
Abstract
Abstract An integrated multi-layer insulator memory cell is produced via silicon-gate technology, with self-adjusting, overlapping polysilicon contact wherein a gate oxide of a peripheral transistor is produced after the application of multi-layer insulating layer comprised of a storage layer and a "blocking" layer. The "blocking" layer consists of an oxynitride layer formed by oxidation of a silicon nitride layer surface or an additionally applied SiO 2 layer and has a layer thickness of about 5 to 30 nm. Such "blocking" layer prevents an undesired injection of charge carriers from the silicon-gate electrode. It also provides means for forming a self-adjusting, overlapping polysilicon contact.
Inventors
- 👤 Ulrich Schwabe
- 👤 Erwin Jacobs
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 14:41
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D30/00; H10D30/60; H10D30/69; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/693; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/8314; H10D88/00; H10D88/01; H10P; H10P76/00; H10P76/40; H10D64/01342; H10D84/83138; Y; Y10; Y10S; Y10S148/00; Y10S148/141; Y10S148/156
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
119 words
A process for producing an integrated multi-insulator memory cell with a self-adjusting overlying polysilicon contact using silicon gate technology comprising applying a relatively thin SiO 2 layer having a thickness of about 1.5 to 12 nm onto the semiconductor substrate and applying an oxynitride layer of a composition (Si x O y N z ) wherein x, y and z are integers having a thickness of about 20 to 60 nm above said SiO 2 layer with said SiO 2 layer functioning as a tunnel oxide and said oxynitride layer functioning as a storage layer, and wherein a gate oxide layer having a thickness of about 50 to 100 nm is produced by a further oxidation of said substrate.
Claim 2
Dependent Claim
119 words
A process for producing an integrated multi-insulator memory cell with a self-adjusting overlying polysilicon contact using silicon gate technology comprising applying a relatively thin SiO 2 layer having a thickness of about 1.5 to 12 nm onto the semiconductor substrate and applying an oxynitride layer of a composition (Si x O y N z ) wherein x, y and z are integers having a thickness of about 20 to 60 nm above said SiO 2 layer with said SiO 2 layer functioning as a tunnel oxide and said oxynitride layer functioning as a storage layer, and wherein a gate oxide layer having a thickness of about 50 to 100 nm is produced by a further oxidation of said substrate.
Claim 3
Dependent Claim
145 words
A process for producing an integrated multi-layer insulator memory cell with a self-adjusting, overlying polysilicon contact using silicon gate technology comprising applying a multi-layer insulator comprising a relatively thin SiO 2 layer having a thickness of about 1.5 to 12 nm onto the surface of the semiconductor substrate and applying at selected locations onto the relatively thin silicon dioxide layer, a silicon nitride layer having a thickness of about 20 to 60 nm wherein said thin silicon dioxide layer functions as a tunnel oxide and said silicon nitride layer functions as a storage layer, producing a gate oxide layer having a thickness of 50 to 100 nm by further oxidation of said substrate, and substantially simultaneously forming an oxynitride layer having a thickness of about 5 to 30 nm by oxidation of said silicon nitride layer and said oxynitride layer functioning as a blocking layer.
Claim 4
Dependent Claim
145 words
A process for producing an integrated multi-layer insulator memory cell with a self-adjusting, overlying polysilicon contact using silicon gate technology comprising applying a multi-layer insulator comprising a relatively thin SiO 2 layer having a thickness of about 1.5 to 12 nm onto the surface of the semiconductor substrate and applying at selected locations onto the relatively thin silicon dioxide layer, a silicon nitride layer having a thickness of about 20 to 60 nm wherein said thin silicon dioxide layer functions as a tunnel oxide and said silicon nitride layer functions as a storage layer, producing a gate oxide layer having a thickness of 50 to 100 nm by further oxidation of said substrate, and substantially simultaneously forming an oxynitride layer having a thickness of about 5 to 30 nm by oxidation of said silicon nitride layer and said oxynitride layer functioning as a blocking layer.
Claim 5
Dependent Claim
38 words
A process as defined in claim 2 wherein a further SiO 2 layer having a thickness of about 5 to 30 nm is applied over said silicon nitride layer, said further oxide layer functioning as a blocking layer.
Claim 6
Dependent Claim
78 words
A process as defined in claim 2 wherein said application of said multi-layer insulator comprises applying an Al 2 O 3 layer having a thickness of about 1.5 to 12 nm onto the semiconductor substrate, and applying a silicon nitride layer having a thickness of about 20 to 60 nm above said Al 2 O 3 layer, said Al 2 O 3 layer functioning as a tunnel oxide and said silicon nitride layer functioning as the storage layer.
Claim 7
Dependent Claim
28 words
A process as defined in claim 4 wherein a Si 3 N 4 -Al 2 O 3 double layer is applied in place of said silicon nitride layer.
Claim 8
Dependent Claim
24 words
A process as defined in claim 4 wherein an AlN-Si 3 N 4 double layer is applied in place of said silicon nitride layer.
Claim 9
Dependent Claim
205 words
A process for producing an integrated multi-layer insulator memory cell with a self-adjusting, overlapping polysilicon contact using silicon-gate technology, comprising, in combination, the sequential steps: (a) producing a structured SiO 2 layer on a semiconductor substrate for separation of active transistor zones from one another according to the LOCOS-process; (b) oxidizing the entire substrate surface with a relatively thin SiO 2 layer, which functions as a tunnel oxide, (c) producing a structured silicon nitride layer in the region of a storage transistor and producing an overlapping contact; (d) applying a gate oxide layer using oxidation and substantially simultaneously transforming the surface of the silicon nitride layer into an oxynitride layer, which functions as a blocking layer; (e) depositing a polysilicon layer onto the entire substrate surface and thereafter structuring such polysilicon layer; (f) producing source-drain zones in said substrate; (g) depositing a silicon dioxide layer over the entire substrate surface and thereafter structuring such silicon dioxide layer so as to function as an intermediate oxide; (h) producing contact holes to the source-drain zones and to the polysilicon layer above the thick oxide zone in said substrate; and (i) depositing metal over the entire surface of said substrate and thereafter structuring such metal layer into contacts.
Claim 10
Dependent Claim
205 words
A process for producing an integrated multi-layer insulator memory cell with a self-adjusting, overlapping polysilicon contact using silicon-gate technology, comprising, in combination, the sequential steps: (a) producing a structured SiO 2 layer on a semiconductor substrate for separation of active transistor zones from one another according to the LOCOS-process; (b) oxidizing the entire substrate surface with a relatively thin SiO 2 layer, which functions as a tunnel oxide, (c) producing a structured silicon nitride layer in the region of a storage transistor and producing an overlapping contact; (d) applying a gate oxide layer using oxidation and substantially simultaneously transforming the surface of the silicon nitride layer into an oxynitride layer, which functions as a blocking layer; (e) depositing a polysilicon layer onto the entire substrate surface and thereafter structuring such polysilicon layer; (f) producing source-drain zones in said substrate; (g) depositing a silicon dioxide layer over the entire substrate surface and thereafter structuring such silicon dioxide layer so as to function as an intermediate oxide; (h) producing contact holes to the source-drain zones and to the polysilicon layer above the thick oxide zone in said substrate; and (i) depositing metal over the entire surface of said substrate and thereafter structuring such metal layer into contacts.
Claim 11
Dependent Claim
22 words
A process as defined in claim 7 wherein said polysilicon layer is deposited in a thickness of about 100 to 1000 nm.
Claim 12
Dependent Claim
21 words
A process as defined in claim 7 wherein at least one peripheral, normal MOS-transistor is produced simultaneously with said memory cell.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-03-23 | 1984-09-22 | 1985-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-03-23 | 1988-09-22 | 1989-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-03-23 | 1992-09-22 | 1993-03-24 | $7700.00 | Window Closed / Lapsed |