Integrated circuit MOS capacitor using implanted region to change threshold

Claim 1

In a semiconductor integrated circuit, an MOS capacitor of the type having: a. a silicon body having a major face and having a predominately P-type original impurity concentration; b. a thin layer of thermal silicon oxide dielectric on a part of the major face; c. a polycrystalline silicon conductive layer overlying said layer of dielectric to provide one plate of a capacitor and means for applying a positive voltage to said conductive layer; d. a capacitor region in the surface of said major face underlying the layer of dielectric to provide the other plate of the capacitor; e. and contact means including a heavily doped N+ region in the silicon body on said one face contiguous with an edge of the capacitor region and providing electrical connection thereo, the improvement wherein: the capacitor region contains ion implanted conductivity-determining impurity material introduced into the silicon in addition to said original impurity concentration to substantially lower the threshold voltage at which said capacitor region inverts thereby causing the MOS capacitor to exhibit a high magnitude of capacitance at voltages applied to the conductive layer which are low compared to the threshold voltage of the device without such conductivity-determining impurity material introduced, the capacitor region being much thinner than the N+ region.