Signal combiner with permuted addressing

Claim 2

A signal processor for processing a set of input signals to a set of output signals comprising: means for sampling said set of input signals at a predetermined output sample rate; means for storing sampled signals of said set of input signals, said storing means containing locations for storing individual ones representing partial sums of said set of input signals, individual ones of said locations being identified by addresses; means coupled to said storing means for combining, by a sequence of operations, signals of said set of input signals with signals stored in locations of said storing means at said predetermined output sample rate; and means coupled to said storing means for providing addresses, said addressing means including means coupled to said combining means for permuting said addresses between sequential ones of said combining operations at the predetermined sample rate of one section of said storing means per output sample interval, said permuted addresses being coupled to said storing means to produce output signals at said output sample rate.

Claim 3

A converter of a set of input signals to a set of output signals comprising: means for sampling said input signals to provide partial sums of said set of input signals over a predetermined sampling period; means for storing said partial sums of said sampled signals in a memory including a plurality of memory sections; address means for providing addresses to said memory for designating locations in said memory for the storing of the partial sums of said sampled signals; means coupled to said memory for combining by a sequence of operations said partial sums of said input signals occurring in said sampling period with the partial sums of signals stored in said memory at locations designated by said addresses to produce combined signals, an output terminal of said combining means being coupled to said memory for storing said combined signals at locations designated by said addresses; said combining means operating on signals of said set of input signals sequentially in a sequence of combining operations, additional ones of said signals of said set of input signals being operated on by a further sequence of said combining operations; and said combining means including means coupled to said address means for permuting said addresses at a rate of one memory section per output sample interval to combine the stored partial sums of a present sequence of input signals with partial sums of an earlier sequence previously stored in said memory thereby to produce a set of said output signals at said output terminal.

Claim 4

A converter of a set of input signals to a set of output signals comprising: means for sampling said input signals to provide partial sums of said set of input signals over a predetermined sampling period; means for storing said partial sums of said sampled signals in a memory including a plurality of memory sections; address means for providing addresses to said memory for designating locations in said memory for the storing of the partial sums of said sampled signals; means coupled to said memory for combining by a sequence of operations said partial sums of said input signals occurring in said sampling period with the partial sums of signals stored in said memory at locations designated by said addresses to produce combined signals, an output terminal of said combining means being coupled to said memory for storing said combined signals at locations designated by said addresses; said combining means operating on signals of said set of input signals sequentially in a sequence of combining operations, additional ones of said signals of said set of input signals being operated on by a further sequence of said combining operations; and said combining means including means coupled to said address means for permuting said addresses at a rate of one memory section per output sample interval to combine the stored partial sums of a present sequence of input signals with partial sums of an earlier sequence previously stored in said memory thereby to produce a set of said output signals at said output terminal.

Claim 5

A converter according to claim 2 wherein said combining means includes weighting means responsive to said addresses for weighting individual ones of said input signals.

Claim 6

A converter according to claim 3 wherein said permuting means includes a counter of said sequences, and means for summing a count of said counter with the address for the said partial sums.

Claim 7

A signal processor comprising: storage means having locations for the storage of signals, each of said locations being identified by an address; arithmetic means; addressing means having a programmable memory coupled to said arithmetic means for providing said addresses to said storage means for designating said locations in said storage means for the storing of signals, said programmable memory activating said arithmetic means to provide mathematical operations between each of a sequence of input signals and the signals stored in said locations designated by said addresses to provide partial sums of output signals at an output terminal of said arithmetic means, said programmable memory activating said arithmetic means to provide said operations for further sequences of said input signals; means for storing said partial sums of said output signals at said designated locations; means coupled to said addressing means for permuting said addresses at a rate of one memory section per output sample interval respectively for each of said sequences of input signals and thus to combine partial sums obtained during successive occurrences of said input signals with succeeding later partial sums; and means for coupling said combined partial sums to an output terminal to produce a completed output sample.

Claim 8

A signal processor comprising: storage means having locations for the storage of signals, each of said locations being identified by an address; arithmetic means; addressing means having a programmable memory coupled to said arithmetic means for providing said addresses to said storage means for designating said locations in said storage means for the storing of signals, said programmable memory activating said arithmetic means to provide mathematical operations between each of a sequence of input signals and the signals stored in said locations designated by said addresses to provide partial sums of output signals at an output terminal of said arithmetic means, said programmable memory activating said arithmetic means to provide said operations for further sequences of said input signals; means for storing said partial sums of said output signals at said designated locations; means coupled to said addressing means for permuting said addresses at a rate of one memory section per output sample interval respectively for each of said sequences of input signals and thus to combine partial sums obtained during successive occurrences of said input signals with succeeding later partial sums; and means for coupling said combined partial sums to an output terminal to produce a completed output sample.

Claim 9

A processor according to claim 5 wherein said addressing means includes a counter and said programmable memory addressed by said counter, said counter counting timing pulses and said programmable memory providing partial addresses in accordance with the count of said counter.

Claim 10

A processor according to claim 6 further comprising a timer producing said timing pulses, and circuit means responsive to said timing pulses for applying said input signals to said arithmetic means.