Serial digital data decoder

Claim 2

A serial digital data decoder comprising: (a) means for receiving a serial data word from a data bus; (b) means for storing said data word as it is received; (c) means for verifying that said data word is addressed to said decoder; (d) means for detecting n consecutive identical data words before enabling an output event specified by said data word; (e) means for inhibiting said output event between consecutive data words when a spurious signal alters said output event data word; and (f) means for deriving timing signals from said data word to operate the internal circuitry of said serial digital data decoder.

Claim 3

A decoder as recited in claim 1 wherein said detecting means comprises: (a) a memory to which is transfered said data word from said storing means after said data word has been verified by said verifying means; (b) a word comparator for comparing said data word from said memory with a consecutive data word from said storing means in parallel; (c) a counter which increments for each identical word comparison detected by said word comparator and which resets when a non-identical comparison is detected; and (d) means for terminating the incrementing of said counter when n consecutive identical data words have been detected and for enabling said output event.

Claim 4

A decoder as recited in claim 2 wherein said inhibiting means comprises: (a) means for decoding said data word from said memory to initiate said output event; and (b) a scramble detector to prevent said decoding means from initiating said output event between said consecutive data words in the event either of the data words contained in said storing means and said memory is scrambled by a spurious signal.

Claim 5

A decoder as recited in claim 3 wherein said deriving means comprises: (a) means for providing timing pulses for each bit of said data word, and for each complete verified data word received; and (b) means for resetting the elements of said decoder after an output event has been completed and when an error is detected.

Claim 6

A decoder as recited in claim 4 wherein said deriving means further comprises: (a) means for determining the end of each of said data words received and for enabling said timing pulses for each complete verified data word; (b) means for restarting said determining means when a missing bit of said data word is detected; (c) means for resetting the internal circuitry of said serial digital data decoder when a subsequent data word is not received within a predetermined time interval, and periodically between data word sequences; and (d) means for disabling said resetting means and said inhibiting means while said data word is being received to prohibit initiation of said output event prior to verification of said data word by said verifying means.

Claim 7

A decoder as recited in claim 1 wherein said receiving means comprises: (a) means for obtaining a data clock strobe from each bit of said data word to input said data word to said storing means; and (b) means for converting the bits of said data word into digital compatible data for storage in said storing means.

Claim 8

A decoder as recited in claim 1 wherein said receiving means further comprises means for triggering said deriving means for each bit of said data word.