Fabrication of an integrated injection logic device with narrow basewidth

Claim 1

A method of fabricating an Integrated Injection Logic device having a lateral PNP transistor with a narrow base width region and a vertical NPN transistor, comprising the steps of: providing a semiconductor body of a given conductivity type, the body having a common boundary surface; depositing a layer of oxide on the common boundary surface; depositing a layer of polycrystalline silicon on the oxide layer; depositing a layer of apertured masking material on the polycrystalline silicon layer; etching the unmasked portions of the polycrystalline silicon layer to expose unetched edges of polycrystalline silicon under the masking layer; doping the exposed edges of the unetched polycrystalline silicon layer to form a narrow line of doped polycrystalline silicon in the polycrystalline silicon layer, the narrow doped line defining the limits of the width of the base region of the PNP transistor; modifying regions of the semiconductor body to an opposite conductivity type to form the emitter and collector regions of the PNP transistor, the collector of the PNP transistor also functioning as the base region of the NPN transistor; depositing a layer of apertured masking material on the layer of oxide, the exposed portions thereof aligned with portions of the collector region of the PNP transistor; modifying the exposed portion of the collector region of the PNP transistor to the given conductivity type to form the collector region of the NPN transistor, the remaining portion of the body of semiconductor material being common to the base region of the PNP transistor and the emitter region of the NPN transistor; and providing each region with respective ohmic contact.

Claim 2

A method of fabricating an Integrated Injection Logic device having a lateral PNP transistor with a narrow base width region and a vertical NPN transistor, comprising the steps of: providing a semiconductor body of a given conductivity type, the body having a common boundary surface; depositing a layer of oxide on the common boundary surface; depositing a layer of polycrystalline silicon on the oxide layer; depositing a layer of apertured masking material on the polycrystalline silicon layer; etching the unmasked portions of the polycrystalline silicon layer to expose unetched edges of polycrystalline silicon under the masking layer; doping the exposed edges of the unetched polycrystalline silicon layer to form a narrow line of doped polycrystalline silicon in the polycrystalline silicon layer, the narrow doped line defining the limits of the width of the base region of the PNP transistor; modifying regions of the semiconductor body to an opposite conductivity type to form the emitter and collector regions of the PNP transistor, the collector of the PNP transistor also functioning as the base region of the NPN transistor; depositing a layer of apertured masking material on the layer of oxide, the exposed portions thereof aligned with portions of the collector region of the PNP transistor; modifying the exposed portion of the collector region of the PNP transistor to the given conductivity type to form the collector region of the NPN transistor, the remaining portion of the body of semiconductor material being common to the base region of the PNP transistor and the emitter region of the NPN transistor; and providing each region with respective ohmic contact.